Issued Patents 2021
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11171221 | VFET bottom epitaxy formed with anchors | Chen Zhang | 2021-11-09 |
| 11164799 | Stacked vertical transport field effect transistor contact formation | Heng Wu, Chen Zhang, Kangguo Cheng | 2021-11-02 |
| 11164791 | Contact formation for stacked vertical transport field-effect transistors | Heng Wu, Chen Zhang, Joshua M. Rubin | 2021-11-02 |
| 11152507 | Vertical field-effect transistor with a bottom contact that exhibits low electrical resistance | Chen Zhang, Terence B. Hook, Brent A. Anderson | 2021-10-19 |
| 11145380 | Analog nonvolatile memory cells using dopant activation | Heng Wu, Oleg Gluschenkov, Alexander Reznicek | 2021-10-12 |
| 11139215 | Hybrid gate stack integration for stacked vertical transport field-effect transistors | Takashi Ando, Oleg Gluschenkov, Chen Zhang, Koji Watanabe | 2021-10-05 |
| 11094784 | Gate-all-around field effect transistor having stacked U shaped channels configured to improve the effective width of the transistor | Kangguo Cheng, Ruilong Xie, Julien Frougier, Chanro Park | 2021-08-17 |
| 11081547 | Method for making superimposed transistors | Shay Reboh, Remi Coquand, Nicolas Loubet, Jingyun Zhang | 2021-08-03 |
| 11069679 | Reducing gate resistance in stacked vertical transport field effect transistors | Heng Wu, Chen Zhang, Kangguo Cheng, Joshua M. Rubin | 2021-07-20 |
| 11062937 | Dielectric isolation for nanosheet devices | Kangguo Cheng, Ruilong Xie, Chun-Chen Yeh | 2021-07-13 |
| 11056570 | Nanosheet transistor with dual inner airgap spacers | Ruilong Xie, Kangguo Cheng, Chun-Chen Yeh | 2021-07-06 |
| 11049933 | Creation of stress in the channel of a nanosheet transistor | Nicolas Loubet, Guillaume Audoit, Nicolas Bernier, Remi Coquand, Shay Reboh | 2021-06-29 |
| 11038041 | Composite spacer enabling uniform doping in recessed fin devices | Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh | 2021-06-15 |
| 11037905 | Formation of stacked vertical transport field effect transistors | Heng Wu, Gen Tsutsui | 2021-06-15 |
| 11018240 | Vertical field effect transistor with reduced parasitic capacitance | Kangguo Cheng, Ruilong Xie, Chun-Chen Yeh | 2021-05-25 |
| 11004856 | Stacked vertical transistor memory cell with epi connections | Chen Zhang, Kangguo Cheng, Heng Wu | 2021-05-11 |
| 10985064 | Buried power and ground in stacked vertical transport field effect transistors | Chen Zhang, Heng Wu, Kangguo Cheng | 2021-04-20 |
| 10964603 | Hybrid gate stack integration for stacked vertical transport field-effect transistors | Takashi Ando, Oleg Gluschenkov, Chen Zhang, Koji Watanabe | 2021-03-30 |
| 10950545 | Circuit wiring techniques for stacked transistor structures | Dongbing Shao, Chen Zhang, Zheng Xu | 2021-03-16 |
| 10937867 | Conformal doping for punch through stopper in fin field effect transistor devices | Huiming Bu, Sivananda K. Kanakasabapathy, Fee Li Lie | 2021-03-02 |
| 10916471 | Dual silicide liner flow for enabling low contact resistance | Praneet Adusumilli, Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh | 2021-02-09 |
| 10916650 | Uniform bottom spacer for VFET devices | Steven R. Bentley, Cheng Chi, Chanro Park, Ruilong Xie | 2021-02-09 |
| 10916640 | Approach to high-k dielectric feature uniformity | Chun Wing Yeung, Chen Zhang | 2021-02-09 |
| 10916468 | Semiconductor device with buried local interconnects | Effendi Leobandung | 2021-02-09 |
| 10903365 | Transistors with uniform source/drain epitaxy | Kangguo Cheng, Ruilong Xie, Chun-Chen Yeh | 2021-01-26 |