Issued Patents 2021
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11164787 | Two-stage top source drain epitaxy formation for vertical field effect transistors enabling gate last formation | Alexander Reznicek, Chun-Chen Yeh, Ruilong Xie | 2021-11-02 |
| 11075280 | Self-aligned gate and junction for VTFET | Kangguo Cheng, Oleg Gluschenkov, Muthumanickam Sankarapandian | 2021-07-27 |
| 11062960 | Shared contact trench comprising dual silicide layers and dual epitaxial layers for source/drain layers of NFET and PFET devices | Heng Wu, Kangguo Cheng, Junli Wang | 2021-07-13 |
| 11038041 | Composite spacer enabling uniform doping in recessed fin devices | Veeraraghavan S. Basker, Tenko Yamashita, Chun-Chen Yeh | 2021-06-15 |
| 11024738 | Measurement of top contact resistance in vertical field-effect transistor devices | Richard Southwick, Xin Miao, Chun Wing Yeung | 2021-06-01 |
| 10985073 | Vertical field effect transistor replacement metal gate fabrication | Ruilong Xie, Wenyu Xu, Brent A. Anderson | 2021-04-20 |
| 10957605 | VFET device design for top contact resistance measurement | Chen Zhang | 2021-03-23 |
| 10950492 | Fabrication of vertical transport fin field effect transistors with a self-aligned separator and an isolation region with an air gap | Kangguo Cheng, Sebastian Naczas, Heng Wu, Peng Xu | 2021-03-16 |
| 10916471 | Dual silicide liner flow for enabling low contact resistance | Praneet Adusumilli, Veeraraghavan S. Basker, Tenko Yamashita, Chun-Chen Yeh | 2021-02-09 |