Issued Patents 2021
Showing 1–25 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11204897 | Importing and exporting circuit layouts | Fu An Tien, Changsheng Ying, Hsu-Ting Huang | 2021-12-21 |
| 11201064 | Signal line patterning for standard cells | Chih-Min HSIAO, Chien-Wen Lai, Chih-Ming Lai, Wei-Shuo Su, Yu-Chen Chang | 2021-12-14 |
| 11175597 | Pellicle structure for lithography mask | Shih-Ming Chang, Chiu-Hsiang Chen, Minfeng Chen | 2021-11-16 |
| 11158509 | Pattern fidelity enhancement with directional patterning technology | Yu-Tien Shen, Chi-Cheng Hung, Chin-Hsiang Lin, Chien-Wei Wang, Ching-Yu Chang +7 more | 2021-10-26 |
| 11127684 | Low-resistance interconnect structures | Chao-Hsun Wang, Wang-Jung Hsueh, Kuo-Yi Chao, Mei-Yun Wang | 2021-09-21 |
| 11106140 | Semiconductor apparatus and method of operating the same | Shih-Ming Chang, Chiu-Hsiang Chen | 2021-08-31 |
| 11093683 | Test pattern generation systems and methods | Fu An Tien, Hsu-Ting Huang | 2021-08-17 |
| 11094556 | Method of manufacturing semiconductor devices using directional process | Ya-Wen Yeh, Yu-Tien Shen, Shih-Chun Huang, Po-Chin Chang, Wei-Liang Lin +4 more | 2021-08-17 |
| 11092899 | Method for mask data synthesis with wafer target adjustment | Hsu-Ting Huang, Tung-Chin Wu, Shih-Hsiang Lo, Chih-Ming Lai, Jue-Chin Yu +1 more | 2021-08-17 |
| 11088030 | Semiconductor device and a method for fabricating the same | Jui-Yao Lai, Sai-Hooi Yeong, Yen-Ming Chen, Yung-Sung Yen, Ying-Yan Chen | 2021-08-10 |
| 11088092 | Via rail solution for high power electromigration | Kam-Tou Sio, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young +3 more | 2021-08-10 |
| 11087994 | Via connection to a partially filled trench | Shih-Ming Chang, Chih-Ming Lai, Tsai-Sheng Gau, Chung-Ju Lee, Tien-I Bao +1 more | 2021-08-10 |
| 11079685 | Method of manufacturing photo masks | Ken-Hsien Hsieh, Wei-Shuo Su | 2021-08-03 |
| 11081354 | Fin patterning methods for increased process margins | Chin-Yuan Tseng, Wei-Liang Lin, Li-Te Lin, Min Cao | 2021-08-03 |
| 11080458 | Lithography simulation method | Fu An Tien, Hsu-Ting Huang, Shih-Hsiang Lo | 2021-08-03 |
| 11075079 | Directional deposition for semiconductor fabrication | Shih-Chun Huang, Ya-Wen Yeh, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang +3 more | 2021-07-27 |
| 11063005 | Via rail solution for high power electromigration | Kam-Tou Sio, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young +3 more | 2021-07-13 |
| 11061318 | Lithography model calibration | Shih-Hsiang Lo, Hsu-Ting Huang | 2021-07-13 |
| 11043381 | Directional patterning method | Po-Chin Chang, Li-Te Lin, Wei-Liang Lin, Pinyen Lin, Yu-Tien Shen +1 more | 2021-06-22 |
| 11043426 | Dummy MOL removal for performance enhancement | Hui-Ting Yang, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young +4 more | 2021-06-22 |
| 11024579 | Dual power structure with connection pins | Shih-Wei Peng, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young +3 more | 2021-06-01 |
| 11018157 | Local interconnect structure | Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young +5 more | 2021-05-25 |
| 11004855 | Buried metal track and methods forming same | Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang +6 more | 2021-05-11 |
| 11004738 | Capacitance reduction by metal cut design | Yi-Hsiung Lin, Yu-Xuan Huang, Chih-Ming Lai, Shang-Wen Chang, Yi-Hsun Chiu | 2021-05-11 |
| 11004729 | Method of manufacturing semiconductor devices | Chin-Hsiang Lin, Chih-Ming Lai, Wei-Liang Lin, Yung-Sung Yen | 2021-05-11 |