Issued Patents 2021
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11188703 | Integrated circuit, system, and method of forming the same | Sang-Chi Huang, Jung-Chan Yang, Pochun Wang | 2021-11-30 |
| 11177256 | Odd-fin height cell regions, semiconductor device having the same, and method of generating a layout diagram corresponding to the same | Ting-Wei Chiang, Chung-Te Lin, Lee-Chung Lu, Li-Chun Tien, Ting Yu Chen | 2021-11-16 |
| 11151297 | Multiple fin count layout, method, system, and device | Po-Chia Lai, Ming-Chang Kuo, Jerry Chang Jui Kao, Wei Ling Chang, Wei-Ren Chen +2 more | 2021-10-19 |
| 11138360 | Semiconductor device with filler cell region, method of generating layout diagram and system for same | Po-Hsiang Huang, Chin-Chou Liu, Sheng-Hsiung Chen, Fong-Yuan Chang, Meng Wang +2 more | 2021-10-05 |
| 11126775 | IC layout, method, device, and system | Shih-Wei Peng, Guo-Huei Wu, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2021-09-21 |
| 11107805 | Integrated circuit | Jian-Sing Li, Guo-Huei Wu, Chih-Liang Chen, Li-Chun Tien | 2021-08-31 |
| 11100273 | Integrated circuit and method of manufacturing same | Shih-Wei Peng, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Shun Li Chen +1 more | 2021-08-24 |
| 11093684 | Power rail with non-linear edge | Jung-Chan Yang, Ting-Wei Chiang, Chi-Yu Lu | 2021-08-17 |
| 11088067 | Semiconductor device and layout design thereof | Chung-Te Lin, Ting-Wei Chiang, Li-Chun Tien, Pin-Dai Sue | 2021-08-10 |
| 11080461 | Method for improved cut metal patterning | Kuang-Ching Chang, Ting-Wei Chiang, Jung-Chan Yang | 2021-08-03 |
| 11075164 | Semiconductor device including a conductive feature over an active region | Tung-Heng Hsieh, Ting-Wei Chiang, Chung-Te Lin, Li-Chun Tien, Sheng-Hsiung Wang | 2021-07-27 |
| 11063045 | Semiconductor device and method of manufacturing the same | Guo-Huei Wu, Jerry Chang Jui Kao, Chih-Liang Chen, Jung-Chan Yang, Lee-Chung Lu +1 more | 2021-07-13 |
| 11050415 | Flip-flop with delineated layout for reduced footprint | Chi-Lin Liu, Ting-Wei Chiang, Jerry Chang Jui Kao, Lee-Chung Lu, Shang-Chih Hsieh +1 more | 2021-06-29 |
| 11048849 | Integrated circuit and method of manufacturing the same | Pochun Wang, Ting-Wei Chiang, Yu-Jung Chang | 2021-06-29 |
| 11037957 | Semiconductor structure | Hsueh-Chih Chou, Chia Hao Tu, Sang Hoo Dhong, Lee-Chung Lu, Li-Chun Tien +1 more | 2021-06-15 |
| 11031334 | Semiconductor device including a conductive feature over an active region | Tung-Heng Hsieh, Ting-Wei Chiang, Chung-Te Lin, Li-Chun Tien, Sheng-Hsiung Wang | 2021-06-08 |
| 11030368 | Metal cut optimization for standard cells | Cheok-Kei Lei, Chi-Lin Liu, Zhe-Wei Jiang, Chi-Yu Lu, Yi-Hsin Ko | 2021-06-08 |
| 11024622 | Integrated circuit having angled conductive feature | Tung-Heng Hsieh, Chung-Te Lin, Sheng-Hsiung Wang, Ting-Wei Chiang, Li-Chun Tien | 2021-06-01 |
| 11004855 | Buried metal track and methods forming same | Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Jung-Chan Yang, Ru-Gun Liu +6 more | 2021-05-11 |
| 10970440 | Method and system for generating layout diagram for semiconductor device having engineering change order (ECO) cells | Mao-Wei Chiu, Ting-Wei Chiang, Li-Chun Tien, Chi-Yu Lu | 2021-04-06 |
| 10971586 | Double height cell regions, semiconductor device having the same, and method of generating a layout diagram corresponding to the same | Jung-Chan Yang, Ting-Wei Chiang, Lee-Chung Lu, Li-Chun Tien | 2021-04-06 |
| 10970451 | Integrated circuit layout method, device, and system | Jian-Sing Li, Ting-Wei Chiang, Jung-Chan Yang, Li-Chun Tien, Ting Yu Chen +1 more | 2021-04-06 |
| 10950594 | Integrated circuit and method of fabricating the same | Chung-Te Lin, Ting-Wei Chiang, Pin-Dai Sue, Li-Chun Tien | 2021-03-16 |
| 10943050 | Capacitive isolation structure insert for reversed signals | Cheok-Kei Lei, Jerry Chang Jui Kao, Chi-Lin Liu, Zhe-Wei Jiang, Chien-Hsing Li | 2021-03-09 |
| 10885254 | Integrated circuit and method of manufacturing same | Ting-Wei Chiang, Li-Chun Tien | 2021-01-05 |