Issued Patents 2021
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11182529 | Semiconductor device including power-grid-adapted route-spacing and method for generating layout diagram of same | Ting-Wei Chiang, Shun Li Chen, Ting Yu Chen, XinYong WANG | 2021-11-23 |
| 11177256 | Odd-fin height cell regions, semiconductor device having the same, and method of generating a layout diagram corresponding to the same | Hui-Zhong Zhuang, Ting-Wei Chiang, Chung-Te Lin, Lee-Chung Lu, Ting Yu Chen | 2021-11-16 |
| 11170152 | Integrated circuit and layout method for standard cell structures | Sheng-Hsiung Chen, Chung-Te Lin, Fong-Yuan Chang, Ho Che Yu | 2021-11-09 |
| 11127673 | Semiconductor device including deep vias, and method of generating layout diagram for same | Ta-Pen Guo, Chien-Ying Chen, Lee-Chung Lu | 2021-09-21 |
| 11107805 | Integrated circuit | Jian-Sing Li, Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen | 2021-08-31 |
| 11088067 | Semiconductor device and layout design thereof | Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue | 2021-08-10 |
| 11081479 | Integrated circuit layout with asymmetric metal lines | Wei-Hsin TSAI, Jung-Chan Yang, Ting Yu Chen | 2021-08-03 |
| 11080453 | Integrated circuit fin layout method, system, and structure | Po-Hsiang Huang, Sheng-Hsiung Chen, Chih-Hsin Ko, Fong-Yuan Chang, Clement Hsingjen Wann +1 more | 2021-08-03 |
| 11075164 | Semiconductor device including a conductive feature over an active region | Tung-Heng Hsieh, Ting-Wei Chiang, Chung-Te Lin, Hui-Zhong Zhuang, Sheng-Hsiung Wang | 2021-07-27 |
| 11037957 | Semiconductor structure | Hsueh-Chih Chou, Chia Hao Tu, Sang Hoo Dhong, Lee-Chung Lu, Ting-Wei Chiang +1 more | 2021-06-15 |
| 11030382 | Integrated circuit with constrained metal line arrangement | XinYong WANG, Yuan Ma, Qiquan Wang | 2021-06-08 |
| 11030372 | Method for generating layout diagram including cell having pin patterns and semiconductor device based on same | Pin-Dai Sue, Chin-Chou Liu, Sheng-Hsiung Chen, Fong-Yuan Chang, Lee-Chung Lu +4 more | 2021-06-08 |
| 11030373 | System for generating standard cell layout having engineering change order (ECO) cells | Ting-Wei Chiang, Shun Li Chen, Ting Yu Chen, XinYong WANG | 2021-06-08 |
| 11031334 | Semiconductor device including a conductive feature over an active region | Tung-Heng Hsieh, Ting-Wei Chiang, Chung-Te Lin, Hui-Zhong Zhuang, Sheng-Hsiung Wang | 2021-06-08 |
| 11024622 | Integrated circuit having angled conductive feature | Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Sheng-Hsiung Wang, Ting-Wei Chiang | 2021-06-01 |
| 11011545 | Semiconductor device including standard cells | Ta-Pen Guo, Lee-Chung Lu | 2021-05-18 |
| 10998340 | Semiconductor device including standard cells having different cell height | Ta-Pen Guo, Lee-Chung Lu | 2021-05-04 |
| 10997348 | Metal cut region location method and system | Jung-Chan Yang, Fong-Yuan Chang, Ting Yu Chen | 2021-05-04 |
| 10970451 | Integrated circuit layout method, device, and system | Jian-Sing Li, Ting-Wei Chiang, Hui-Zhong Zhuang, Jung-Chan Yang, Ting Yu Chen +1 more | 2021-04-06 |
| 10971586 | Double height cell regions, semiconductor device having the same, and method of generating a layout diagram corresponding to the same | Jung-Chan Yang, Ting-Wei Chiang, Hui-Zhong Zhuang, Lee-Chung Lu | 2021-04-06 |
| 10970440 | Method and system for generating layout diagram for semiconductor device having engineering change order (ECO) cells | Mao-Wei Chiu, Ting-Wei Chiang, Hui-Zhong Zhuang, Chi-Yu Lu | 2021-04-06 |
| 10950594 | Integrated circuit and method of fabricating the same | Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue | 2021-03-16 |
| 10885254 | Integrated circuit and method of manufacturing same | Ting-Wei Chiang, Hui-Zhong Zhuang | 2021-01-05 |