Issued Patents 2021
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11201243 | Nanowire stack GAA device and methods for producing the same | Chansyun David Yang, Han-Yu Lin, Chun-Yu Chen, Chih-Ching Wang, Fang-Wei Lee +3 more | 2021-12-14 |
| 11195759 | Semiconductor arrangement and method for making | Wei-Lun Chen, Chao-Hsien Huang, Li-Te Lin | 2021-12-07 |
| 11183580 | Structure and formation method of semiconductor device with metal gate stack | Jung-Hao Chang, Li-Te Lin | 2021-11-23 |
| 11152491 | Method for forming semiconductor device structure with inner spacer layer | Han-Yu Lin, Chansyun David Yang, Fang-Wei Lee, Tze-Chung Lin, Li-Te Lin | 2021-10-19 |
| 11107904 | Inner spacer formation in multi-gate transistors | Han-Yu Lin, Chansyun David Yang, Tze-Chung Lin, Fang-Wei Lee, Fo-Ju Lin +1 more | 2021-08-31 |
| 11094556 | Method of manufacturing semiconductor devices using directional process | Ya-Wen Yeh, Yu-Tien Shen, Shih-Chun Huang, Po-Chin Chang, Wei-Liang Lin +4 more | 2021-08-17 |
| 11056393 | Method for FinFET fabrication and structure thereof | Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Tze-Chung Lin, Chao-Hsien Huang +2 more | 2021-07-06 |
| 11043381 | Directional patterning method | Po-Chin Chang, Li-Te Lin, Ru-Gun Liu, Wei-Liang Lin, Yu-Tien Shen +1 more | 2021-06-22 |
| 11024721 | Semiconductor device and manufacturing method thereof | Zhi-Qiang WU, Kuo-An Liu, Chan-Lon Yang, Bharath Kumar Pulicherla, Li-Te Lin +2 more | 2021-06-01 |
| 10998421 | Reducing pattern loading in the etch-back of metal gate | Po-Chin Chang, Wei-Hao Wu, Li-Te Lin | 2021-05-04 |
| 10957779 | Gate etch back with reduced loading effect | Yi-Chen Lo, Jung-Hao Chang, Li-Te Lin | 2021-03-23 |
| 10950434 | Methods of reducing gate spacer loss during semiconductor manufacturing | Yi-Ruei Jhan, Han-Yu Lin, Li-Te Lin | 2021-03-16 |