Issued Patents 2017
Showing 51–75 of 101 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9679883 | Hollow metal pillar packaging scheme | Chang-Pin Huang, Hsien-Ming Tu, Tung-Liang Shao, Ching-Jung Yang, Yu-Chia Lai | 2017-06-13 |
| 9679839 | Chip on package structure and method | An-Jhih Su, Der-Chyang Yeh | 2017-06-13 |
| 9679868 | Ball height control in bonding process | Tsung-Yuan Yu, Jie Chen | 2017-06-13 |
| 9673160 | Packaging devices, methods of manufacture thereof, and packaging methods | Tsung-Yuan Yu | 2017-06-06 |
| 9666522 | Alignment mark design for packages | Li-Hsien Huang, Ching-Wen Hsiao, Der-Chyang Yeh, Shin-Puu Jeng, Chen-Hua Yu | 2017-05-30 |
| 9666502 | Discrete polymer in fan-out packages | Jie Chen | 2017-05-30 |
| 9659863 | Semiconductor devices, multi-die packages, and methods of manufacture thereof | Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Shih-Peng Tai | 2017-05-23 |
| 9659890 | Methods and apparatus of packaging semiconductor devices | Chia-Wei Tu, Yian-Liang Kuo, Tsung-Fu Tsai, Ru-Ying Huang, Ming-Song Sheu | 2017-05-23 |
| 9659878 | Wafer level shielding in multi-stacked fan out packages and methods of forming same | Wei-Yu Chen, An-Jhih Su, Jo-Mei Wang, Tien-Chung Yang | 2017-05-23 |
| 9646941 | Semiconductor packaging device including via-in pad (VIP) and manufacturing method thereof | Ying-Ju Chen | 2017-05-09 |
| 9647054 | Inductor system and method | Hao-Yi Tsai, Hung-Yi Kuo, Tsung-Yuan Yu | 2017-05-09 |
| 9646954 | Integrated circuit with test circuit | Shih-Wei Liang, Yu-Wen Liu | 2017-05-09 |
| 9646944 | Alignment structures and methods of forming same | Ching-Jung Yang | 2017-05-09 |
| 9640496 | Semiconductor device | Wei-Yu Chen, An-Jhih Su, Cheng-Hsien Hsieh | 2017-05-02 |
| 9633961 | Packaging devices and methods of manufacture thereof | Jie Chen | 2017-04-25 |
| 9633963 | Packaging devices and methods of manufacture thereof | Tsung-Yuan Yu, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu | 2017-04-25 |
| 9633870 | System and method for an improved interconnect structure | Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu, Tsung-Yuan Yu | 2017-04-25 |
| 9627290 | Bump structure design for stress reduction | — | 2017-04-18 |
| 9627288 | Package structures and methods of forming the same | Wei-Yu Chen, Cheng-Hsien Hsieh | 2017-04-18 |
| 9620482 | Semiconductor device and manufacturing method thereof | Yu-Jen Chen, Der-Chyang Yeh | 2017-04-11 |
| 9620469 | Mechanisms for forming post-passivation interconnect structure | Ying-Ju Chen | 2017-04-11 |
| 9613910 | Anti-fuse on and/or in package | An-Jhih Su | 2017-04-04 |
| 9613931 | Fan-out stacked system in package (SIP) having dummy dies and methods of making the same | Tsung-Shu Lin, Cheng-Chieh Hsieh, Chang-Chia Huang | 2017-04-04 |
| 9613914 | Post-passivation interconnect structure | Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu | 2017-04-04 |
| 9613857 | Electrostatic discharge protection structure and method | Jie Chen | 2017-04-04 |