Issued Patents All Time
Showing 26–50 of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10867963 | Die stack structure and method of fabricating the same | Chia-Hao Hsu, Chien-Ming Chiu, Tsang-Jiuh Wu, Wen-Chih Chiou | 2020-12-15 |
| 10867985 | Method and structure of three-dimensional chip stacking | Chen-Hua Yu, Wen-Chih Chiou | 2020-12-15 |
| 10811374 | Interconnect structure and method of forming same | Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Ku-Feng Yang +2 more | 2020-10-20 |
| 10714423 | Through via structure and method | Hsin-Yu Chen, Lin-Chih Huang, Tsang-Jiuh Wu, Wen-Chih Chiou | 2020-07-14 |
| 10535586 | Robust through-silicon-via structure | Tsang-Jiuh Wu, Wen-Chih Chiou | 2020-01-14 |
| 10515940 | Method and structure of three-dimensional chip stacking | Chen-Hua Yu, Wen-Chih Chiou | 2019-12-24 |
| 10510641 | Semiconductor device having backside interconnect structure on through substrate via and method of forming the same | Hsin-Yu Chen, Ming-Tsu Chung, HsiaoYun Lo, Hong-Ye Shih, Chia-Yin Chen +3 more | 2019-12-17 |
| 10497619 | Method of manufacturing a semiconductor device including through silicon plugs | Chen-Hua Yu, Chia-Lin Yu, Hung-Pin Chang, Chien Ling Hwang, Jui-Pin Hung | 2019-12-03 |
| 10396014 | Robust through-silicon-via structure | Tsang-Jiuh Wu, Wen-Chih Chiou | 2019-08-27 |
| 10297550 | 3D IC architecture with interposer and interconnect structure for bonding dies | Hsien-Pin Hu, Chen-Hua Yu, Ming-Fa Chen, Jing-Cheng Lin, Jiun-Ren Lai | 2019-05-21 |
| 10157866 | Interconnect structure and method of forming same | Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Ku-Feng Yang +2 more | 2018-12-18 |
| 10068789 | Method of using a wafer cassette to charge an electrostatic carrier | Wen-Chih Chiou, Yu-Liang Lin, Hung-Jung Tu | 2018-09-04 |
| 10049931 | Method of manufacturing a semiconductor device including through silicon plugs | Chen-Hua Yu, Hung-Pin Chang, Chia-Lin Yu, Jui-Pin Hung, Chien Ling Hwang | 2018-08-14 |
| 10032698 | Interconnection structure with confinement layer | Hsiao Yun Lo, Yang-Chih Hsueh, Tsang-Jiuh Wu, Wen-Chih Chiou | 2018-07-24 |
| 9978607 | Through via structure and method | Hung-Pin Chang, Tsang-Jiuh Wu, Wen-Chih Chiou | 2018-05-22 |
| 9922934 | Semiconductor manufacturing process and package carrier | Shih-Hui Wang, Chih-Hung Cheng, Wen-Chih Chiou | 2018-03-20 |
| 9865523 | Robust through-silicon-via structure | Tsang-Jiuh Wu, Wen-Chih Chiou | 2018-01-09 |
| 9847255 | TSV formation processes using TSV-last approach | Jing-Cheng Lin, Ku-Feng Yang | 2017-12-19 |
| 9847256 | Methods for forming a device having a capped through-substrate via structure | Yen-Hung Chen, Yin Chen, Ebin Liao, Ku-Feng Yang, Tsang-Jiuh Wu +1 more | 2017-12-19 |
| 9831177 | Through via structure | Hsin-Yu Chen, Lin-Chih Huang, Tsang-Jiuh Wu, Wen-Chih Chiou | 2017-11-28 |
| 9773768 | Method and structure of three-dimensional chip stacking | Chen-Hua Yu, Wen-Chih Chiou | 2017-09-26 |
| 9754831 | Dummy structure for chip-on-wafer-on-substrate | Pei-Ching Kuo, Yi-Hsiu Chen, Jun-Lin Yeh, Li-Han Hsu, Wei-Cheng Wu +2 more | 2017-09-05 |
| 9679859 | Interconnect structure and method of forming same | Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Ku-Feng Yang +2 more | 2017-06-13 |
| 9673132 | Interconnection structure with confinement layer | Hsiao Yun Lo, Yang-Chih Hsueh, Tsang-Jiuh Wu, Wen-Chih Chiou | 2017-06-06 |
| 9570331 | Wafer cassette with electrostatic carrier charging scheme | Wen-Chih Chiou, Yu-Liang Lin, Hung-Jung Tu | 2017-02-14 |