Issued Patents All Time
Showing 26–50 of 89 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11881452 | Device layer interconnects | Mark Bohr, Marni Nabors | 2024-01-23 |
| 11830788 | Integrated circuits and methods for forming integrated circuits | Carl Naylor, Ashish Agrawal, Urusa Alaan, Christopher J. Jezewski, Kevin Lin +1 more | 2023-11-28 |
| 11817442 | Hybrid manufacturing for integrated circuit devices and assemblies | Wilfred Gomes, Abhishek A. Sharma, Doug B. Ingerly | 2023-11-14 |
| 11799037 | Gate-all-around integrated circuit structures having asymmetric source and drain contact structures | Biswajeet Guha, Tahir Ghani | 2023-10-24 |
| 11756886 | Hybrid manufacturing of microeletronic assemblies with first and second integrated circuit structures | Wilfred Gomes, Abhishek A. Sharma, Doug B. Ingerly | 2023-09-12 |
| 11721554 | Stress compensation for wafer to wafer bonding | Anant H. JAHAGIRDAR, Chytra Pawashe, Aaron D. Lilak, Myra McDonnell, Brennen Mueller | 2023-08-08 |
| 11690211 | Thin film transistor based memory cells on both sides of a layer of logic devices | Wilfred Gomes, Conor P. Puls, Kevin J. Fischer, Bernhard Sell, Abhishek A. Sharma +1 more | 2023-06-27 |
| 11621354 | Integrated circuit structures having partitioned source or drain contact structures | Stephanie A. Bojarski, Babita Dhayal, Biswajeet Guha, Tahir Ghani | 2023-04-04 |
| 11616015 | Integrated circuit device with back-side interconnection to deep source/drain semiconductor | Patrick Morrow, Mark Bohr, Tahir Ghani, Rishabh Mehandru | 2023-03-28 |
| 11532558 | Metallization barrier structures for bonded integrated circuit interfaces | Carl Naylor, Richard Vreeland, Ramanan V. Chebiam, William Brezinski, Brennen Mueller +1 more | 2022-12-20 |
| 11444166 | Backside source/drain replacement for semiconductor devices with metallization on both sides | Glenn A. Glass, Karthik Jambunathan, Anand S. Murthy, Chandra S. Mohapatra, Patrick Morrow | 2022-09-13 |
| 11410928 | Device layer interconnects | Mark Bohr, Marni Nabors | 2022-08-09 |
| 11373999 | Deep trench via for three-dimensional integrated circuit | Yih Wang, Rishabh Mehandru, Tahir Ghani, Mark Bohr, Marni Nabors | 2022-06-28 |
| 11367796 | Gate-all-around integrated circuit structures having asymmetric source and drain contact structures | Biswajeet Guha, Tahir Ghani | 2022-06-21 |
| 11335686 | Transistors with back-side contacts to create three dimensional memory and logic | Wilfred Gomes, Abhishek A. Sharma, Tahir Ghani, Doug B. Ingerly, Rajesh Kumar | 2022-05-17 |
| 11329162 | Integrated circuit structures having differentiated neighboring partitioned source or drain contact structures | Stephanie A. Bojarski, Myra McDonnell, Tahir Ghani | 2022-05-10 |
| 11328951 | Transistor cells including a deep via lined wit h a dielectric material | Patrick Morrow, Rishabh Mehandru | 2022-05-10 |
| 11276644 | Integrated circuits and methods for forming thin film crystal layers | Carl Naylor, Ashish Agrawal, Kevin Lin, Abhishek A. Sharma, Christopher J. Jezewski +1 more | 2022-03-15 |
| 11257822 | Three-dimensional nanoribbon-based dynamic random-access memory | Wilfred Gomes, Kinyip Phoa, Tahir Ghani, Uygar E. Avci, Rajesh Kumar | 2022-02-22 |
| 11239238 | Thin film transistor based memory cells on both sides of a layer of logic devices | Wilfred Gomes, Conor P. Puls, Kevin J. Fischer, Bernhard Sell, Abhishek A. Sharma +1 more | 2022-02-01 |
| 11189585 | Selective recess of interconnects for probing hybrid bond devices | Brennen Mueller, Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Pooya Tadayon | 2021-11-30 |
| 11171239 | Transistor channel passivation with 2D crystalline material | Carl Naylor, Abhishek A. Sharma, Christopher J. Jezewski, Urusa Alaan, Justin R. Weber | 2021-11-09 |
| 11164809 | Integrated circuits and methods for forming integrated circuits | Carl Naylor, Ashish Agrawal, Kevin Lin, Abhishek A. Sharma, Christopher J. Jezewski +1 more | 2021-11-02 |
| 11139241 | Integrated circuit device with crenellated metal trace layout | Patrick Morrow, Mark Bohr, Tahir Ghani, Rishabh Mehandru, Ranjith Kumar | 2021-10-05 |
| 11139300 | Three-dimensional memory arrays with layer selector transistors | Wilfred Gomes, Abhishek A. Sharma, Rajesh Kumar, Kinyip Phoa, Elliot N. Tan +2 more | 2021-10-05 |