Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12317590 | Substrate-free integrated circuit structures | Biswajeet Guha, Brian J. Greene, Avyaya Jayanthinarasimham, Ayan Kar, Benjamin Orr +9 more | 2025-05-27 |
| 12170273 | Integrated circuit assemblies with direct chip attach to circuit boards | Wilfred Gomes, Sanka Ganesan, Abhishek A. Sharma, Doug B. Ingerly, Mauro J. Kobrinsky | 2024-12-17 |
| 12166031 | Substrate-less electrostatic discharge (ESD) integrated circuit structures | Biswajeet Guha, Brian J. Greene, Daniel Schulman, William Hsu, Chung-Hsun Lin +1 more | 2024-12-10 |
| 11690211 | Thin film transistor based memory cells on both sides of a layer of logic devices | Wilfred Gomes, Mauro J. Kobrinsky, Conor P. Puls, Bernhard Sell, Abhishek A. Sharma +1 more | 2023-06-27 |
| 11239238 | Thin film transistor based memory cells on both sides of a layer of logic devices | Wilfred Gomes, Mauro J. Kobrinsky, Conor P. Puls, Bernhard Sell, Abhishek A. Sharma +1 more | 2022-02-01 |
| 10593626 | AVD hardmask for damascene patterning | Ruth A. Brain, Michael A. Childs | 2020-03-17 |
| 10229879 | Thickened stress relief and power distribution layer | Christopher M. Pelto, Andrew W. Yeoh | 2019-03-12 |
| 9984922 | Interconnects having sealing structures to enable selective metal capping layers | Jun He, Ying Zhou, Peter K. Moon | 2018-05-29 |
| 9780038 | AVD hardmask for damascene patterning | Ruth A. Brain, Michael A. Childs | 2017-10-03 |
| 9627312 | On-chip capacitors and methods of assembling same | Michael A. Childs, Sanjay Natarajan | 2017-04-18 |
| 9502281 | AVD hardmask for damascene patterning | Ruth A. Brain, Michael A. Childs | 2016-11-22 |
| 9496173 | Thickened stress relief and power distribution layer | Christopher M. Pelto, Andrew W. Yeoh | 2016-11-15 |
| 9437545 | Interconnects having sealing structures to enable selective metal capping layers | Jun He, Ying Zhou, Peter K. Moon | 2016-09-06 |
| 9123727 | Airgap interconnect with hood layer and method of forming | — | 2015-09-01 |
| 8987859 | Techniques for enhancing dielectric breakdown performance | Pavel S. Plekhanov, Qiang Fu, Hiroki Hiramatsu | 2015-03-24 |
| 8928125 | Interconnects having sealing structures to enable selective metal capping layers | Jun He, Ying Zhou, Peter K. Moon | 2015-01-06 |
| 8827550 | Thermal sensor using a vibrating MEMS resonator of a chip interconnect layer | Mohamed A. Abdelmoneum, Tawfik M. Rahal-Arabi, Gregory F. Taylor, Andrew W. Yeoh | 2014-09-09 |
| 8278718 | Stressed barrier plug slot contact structure for transistor performance enhancement | Vinay Chikarmane, Brennan Peterson | 2012-10-02 |
| 8120119 | Stressed barrier plug slot contact structure for transistor performance enhancement | Vinay Chikarmane, Brennan Peterson | 2012-02-21 |
| 8058710 | Interconnects having sealing structures to enable selective metal capping layers | Jun He, Ying Zhou, Peter K. Moon | 2011-11-15 |
| 7968952 | Stressed barrier plug slot contact structure for transistor performance enhancement | Vinay Chikarmane, Brennan Peterson | 2011-06-28 |
| 7768126 | Barrier formation and structure to use in semiconductor devices | Vinay Chikarmane, Brennan Peterson | 2010-08-03 |
| 7719062 | Tuned tensile stress low resistivity slot contact structure for n-type transistor performance enhancement | Vinay Chikarmane, Brennan Peterson | 2010-05-18 |
| 7582558 | Reducing corrosion in copper damascene processes | Vinay Chikarmane, Brennan Peterson | 2009-09-01 |
| 7525197 | Barrier process/structure for transistor trench contact applications | Vinay Chikarmane, Brennan Peterson | 2009-04-28 |