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USPTO Patent Rankings Data through Dec 31, 2025
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Vinay Chikarmane — 16 Patents

Intel: 16 patents #2,596 of 30,777Top 9%
Portland, OR: #1,150 of 9,213 inventorsTop 15%
Oregon: #2,717 of 28,073 inventorsTop 10%
Overall (All Time): #284,196 of 4,157,543Top 7%
16 Patents All Time
Vinay Chikarmane has been granted 16 US patents while listed as an inventor at Intel. The first was granted in 1998 and the most recent in April 2024. Vinay Chikarmane ranks #284,196 of 4,157,543 US inventors in our database (top 6.8%). Patent records list Vinay Chikarmane in Portland, OR, US.

Issued Patents All Time

Showing 1–16 of 16 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11955534 Heterogeneous metal line compositions for advanced integrated circuit structure fabrication Andrew W. Yeoh, Joseph M. Steigerwald, Jinhong SHIN, Christopher P. Auth 2024-04-09 $27,197,000
11581419 Heterogeneous metal line compositions for advanced integrated circuit structure fabrication Andrew W. Yeoh, Joseph M. Steigerwald, Jinhong SHIN, Christopher P. Auth 2023-02-14 $12,790,000
10854731 Heterogeneous metal line compositions for advanced integrated circuit structure fabrication Andrew W. Yeoh, Joseph M. Steigerwald, Jinhong SHIN, Christopher P. Auth 2020-12-01 $25,476,000
10777655 Heterogeneous metal line compositions for advanced integrated circuit structure fabrication Andrew W. Yeoh, Joseph M. Steigerwald, Jinhong SHIN, Christopher P. Auth 2020-09-15 $34,212,000
8278718 Stressed barrier plug slot contact structure for transistor performance enhancement Kevin J. Fischer, Brennan Peterson 2012-10-02 $10,164,000
8120119 Stressed barrier plug slot contact structure for transistor performance enhancement Kevin J. Fischer, Brennan Peterson 2012-02-21 $21,312,000
7968952 Stressed barrier plug slot contact structure for transistor performance enhancement Kevin J. Fischer, Brennan Peterson 2011-06-28 $18,630,000
7768126 Barrier formation and structure to use in semiconductor devices Kevin J. Fischer, Brennan Peterson 2010-08-03 $10,607,000
7741219 Method for manufacturing a semiconductor device using the self aligned contact (SAC) process flow for semiconductor devices with aluminum metal gates Yang Cao 2010-06-22 $25,275,000
7719062 Tuned tensile stress low resistivity slot contact structure for n-type transistor performance enhancement Kevin J. Fischer, Brennan Peterson 2010-05-18 $11,091,000
7582558 Reducing corrosion in copper damascene processes Kevin J. Fischer, Brennan Peterson 2009-09-01 $29,239,000
7525197 Barrier process/structure for transistor trench contact applications Kevin J. Fischer, Brennan Peterson 2009-04-28 $19,079,000
7371311 Modified electroplating solution components in a low-acid electrolyte solution Daniel J. Zierath, Valery M. Dubin 2008-05-13 $17,373,000
7070687 Apparatus and method of surface treatment for electrolytic and electroless plating of metals in integrated circuit manufacturing Chi-Hwa Tsang 2006-07-04
7001641 Seed layer treatment Valery M. Dubin, Christopher D. Thomas 2006-02-21 $16,743,000
5804251 Low temperature aluminum alloy plug technology Jick Yu 1998-09-08 $57,567,000