Issued Patents All Time
Showing 326–350 of 605 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10381563 | Resistive memory crossbar array compatible with Cu metallization | Michael Rizzolo, Lawrence A. Clevenger, Shyng-Tsong Chen | 2019-08-13 |
| 10381561 | Dedicated contacts for controlled electroforming of memory cells in resistive random-access memory array | Lawrence A. Clevenger, Chih-Chao Yang, Benjamin D. Briggs | 2019-08-13 |
| 10381438 | Vertically stacked NFETS and PFETS with gate-all-around structure | Jingyun Zhang, Pouya Hashemi, Choonghyun Lee, Alexander Reznicek | 2019-08-13 |
| 10377370 | Hybrid vehicle | Yu Shimizu, Takeshi Kishimoto, Masaya Amano | 2019-08-13 |
| 10381433 | Leakage current reduction in stacked metal-insulator-metal capacitors | Hemanth Jagannathan, Paul C. Jamison, John Rozen | 2019-08-13 |
| 10381431 | Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS back-end | Martin M. Frank, Xiao Sun, Jin-Ping Han, Vijay Narayanan | 2019-08-13 |
| 10374039 | Enhanced field bipolar resistive RAM integrated with FDSOI technology | Pouya Hashemi, Alexander Reznicek | 2019-08-06 |
| 10373835 | Method of lateral oxidation of nFET and pFET high-K gate stacks | Robert H. Dennard, Martin M. Frank | 2019-08-06 |
| 10366323 | Crossbar resistive memory array with highly conductive copper/copper alloy electrodes and silver/silver alloys electrodes | Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe | 2019-07-30 |
| 10366897 | Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer | Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan | 2019-07-30 |
| 10361281 | Method to improve reliability of replacement gate device | Eduard A. Cartier, Kisik Choi, Vijay Narayanan | 2019-07-23 |
| 10361132 | Structures with thinned dielectric material | Ruqiang Bao, Aritra Dasgupta, Kai Zhao, Unoh Kwon, Siddarth A. Krishnan | 2019-07-23 |
| 10361131 | Stacked field-effect transistors (FETs) with shared and non-shared gates | Pouya Hashemi, Choonghyun Lee, Alexander Reznicek, Jingyun Zhang | 2019-07-23 |
| 10361093 | Multi time programmable memories using local implantation in high-K/ metal gate technologies | Eduard A. Cartier, Chandrasekharan Kothandaraman | 2019-07-23 |
| 10361237 | Low dark current backside illumination sensor | Choonghyun Lee | 2019-07-23 |
| 10361368 | Confined lateral switching cell for high density scaling | Robert L. Bruce, John Rozen | 2019-07-23 |
| 10361367 | Resistive memory crossbar array with top electrode inner spacers | Hiroyuki Miyazoe, Iqbal Rashid Saraf, Shyng-Tsong Chen | 2019-07-23 |
| 10347494 | Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer | Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan | 2019-07-09 |
| 10332957 | Stacked capacitor with symmetric leakage and break-down behaviors | Eduard A. Cartier, Vijay Narayanan, Adam M. Pyzyna | 2019-06-25 |
| 10332809 | Method and structure to introduce strain in stack nanosheet field effect transistor | Jingyun Zhang, Choonghyun Lee, Pouya Hashemi, Alexander Reznicek | 2019-06-25 |
| 10332971 | Replacement metal gate stack for diffusion prevention | Johnathan E. Faltermeier, Su Chen Fan, Sivananda K. Kanakasabapathy, Injo Ok, Tenko Yamashita | 2019-06-25 |
| 10319596 | Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer | Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan | 2019-06-11 |
| 10319818 | Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS front-end | Martin M. Frank, Xiao Sun, Jin-Ping Han, Vijay Narayanan | 2019-06-11 |
| 10319826 | Replacement metal gate stack with oxygen and nitrogen scavenging layers | Pouya Hashemi, Choonghyun Lee | 2019-06-11 |
| 10319846 | Multiple work function nanosheet field-effect transistors with differential interfacial layer thickness | Choonghyun Lee, Jingyun Zhang, Pouya Hashemi | 2019-06-11 |