Issued Patents All Time
Showing 301–325 of 605 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10553679 | Formation of self-limited inner spacer for gate-all-around nanosheet FET | Jingyun Zhang, Choonghyun Lee, Alexander Reznicek, Pouya Hashemi | 2020-02-04 |
| 10553696 | Full air-gap spacers for gate-all-around nanosheet field effect transistors | Pouya Hashemi, Choonghyun Lee, Alexander Reznicek, Jingyun Zhang | 2020-02-04 |
| 10553584 | Patterned gate dielectrics for III-V-based CMOS circuits | Martin M. Frank, Renee T. Mo, Vijay Narayanan, John Rozen | 2020-02-04 |
| 10546892 | Resistive memory device with meshed electrodes | Lawrence A. Clevenger, Chih-Chao Yang, Michael Rizzolo | 2020-01-28 |
| 10546925 | Vertically stacked nFET and pFET with dual work function | Alexander Reznicek, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi | 2020-01-28 |
| 10533076 | Resin composition and method for producing pearly molded body | Kazutaka Katayama, Junichi Yoshioka | 2020-01-14 |
| 10535606 | Dual metal-insulator-semiconductor contact structure and formulation method | Hiroaki Niimi, Tenko Yamashita | 2020-01-14 |
| 10535570 | Cointegration of III-V channels and germanium channels for vertical field effect transistors | Pouya Hashemi, Choonghyun Lee | 2020-01-14 |
| 10529798 | Multiple work function device using GeOx/TiN cap on work function setting metal | Pouya Hashemi, Choonghyun Lee | 2020-01-07 |
| 10529716 | Asymmetric threshold voltage VTFET with intrinsic dual channel epitaxy | Choonghyun Lee, Jingyun Zhang, Alexander Reznicek, Pouya Hashemi | 2020-01-07 |
| 10529573 | Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device | Pouya Hashemi, Hemanth Jagannathan, Choonghyun Lee, Vijay Narayanan | 2020-01-07 |
| 10529815 | Conformal replacement gate electrode for short channel devices | Ruqiang Bao, Masanobu Hatanaka, Vijay Narayanan, Yohei Ogawa, John Rozen | 2020-01-07 |
| 10522419 | Stacked field-effect transistors (FETs) with shared and non-shared gates | Pouya Hashemi, Choonghyun Lee, Alexander Reznicek, Jingyun Zhang | 2019-12-31 |
| 10504799 | Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap | Martin M. Frank, Renee T. Mo, Vijay Narayanan | 2019-12-10 |
| 10505112 | CMOS compatible non-filamentary resistive memory stack | Eduard A. Cartier, Adam M. Pyzyna, John Bruley | 2019-12-10 |
| 10504900 | Enhanced field Resistive RAM integrated with nanosheet technology | Pouya Hashemi, Alexander Reznicek | 2019-12-10 |
| 10497752 | Resistive random-access memory array with reduced switching resistance variability | Choonghyun Lee, Seyoung Kim, Wilfried E. Haensch | 2019-12-03 |
| 10490559 | Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions | Ruqiang Bao, Pouya Hashemi, Choonghyun Lee | 2019-11-26 |
| 10475997 | Forming resistive memory crossbar array employing selective barrier layer growth | Chih-Chao Yang, Lawrence A. Clevenger | 2019-11-12 |
| 10453792 | High density antifuse co-integrated with vertical FET | Alexander Reznicek, Pouya Hashemi, Miaomiao Wang | 2019-10-22 |
| 10396126 | Resistive memory device with electrical gate control | Seyoung Kim, Choonghyun Lee, Injo Ok, Soon-Cheon Seo | 2019-08-27 |
| 10395993 | Methods and structure to form high K metal gate stack with single work-function metal | Balaji Kannan, Siddarth A. Krishnan, Unoh Kwon, Shahab Siddiqui | 2019-08-27 |
| 10396077 | Patterned gate dielectrics for III-V-based CMOS circuits | Martin M. Frank, Renee T. Mo, Vijay Narayanan, John Rozen | 2019-08-27 |
| 10396146 | Leakage current reduction in stacked metal-insulator-metal capacitors | Hemanth Jagannathan, Paul C. Jamison, John Rozen | 2019-08-27 |
| 10388727 | Stacked indium gallium arsenide nanosheets on silicon with bottom trapezoid isolation | Pouya Hashemi, Mahmoud Khojasteh, Alexander Reznicek | 2019-08-20 |