Issued Patents All Time
Showing 101–122 of 122 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8679941 | Method to improve wet etch budget in FEOL integration | Jason E. Cummings, Lisa F. Edge, Balasubramanian S. Haran, David V. Horak, Hemanth Jagannathan | 2014-03-25 |
| 8652950 | C-rich carbon boron nitride dielectric films for use in electronic devices | Son V. Nguyen, Alfred Grill, Thomas J. Haigh, Jr. | 2014-02-18 |
| 8617961 | Post-gate isolation area formation for fin field effect transistor device | Balasubramanian S. Haran, Theodorus E. Standaert | 2013-12-31 |
| 8614486 | Low resistance source and drain extensions for ETSOI | Balasubramanian S. Haran, Hemanth Jagannathan, Sivananda K. Kanakasabapathy | 2013-12-24 |
| 8551872 | Low series resistance transistor structure on silicon on insulator layer | Kangguo Chen, Bruce B. Doris, Balasubramanian S. Haran, Amlan Majumdar | 2013-10-08 |
| 8535999 | Stress memorization process improvement for improved technology performance | Lahir Shaik Adam, Bruce B. Doris, Zhengmao Zhu | 2013-09-17 |
| 8486778 | Low resistance source and drain extensions for ETSOI | Balasubramanian S. Haran, Hemanth Jagannathan, Sivananda K. Kanakasabapathy | 2013-07-16 |
| 8476743 | C-rich carbon boron nitride dielectric films for use in electronic devices | Son V. Nguyen, Alfred Grill, Thomas J. Haigh, Jr. | 2013-07-02 |
| 8440552 | Method to form low series resistance transistor devices on silicon on insulator layer | Kangguo Chen, Bruce B. Doris, Balasubramanian S. Haran, Amlan Majumdar | 2013-05-14 |
| 8394684 | Structure and method for stress latching in non-planar semiconductor devices | Sivananda K. Kanakasabapathy, Hemanth Jagannathan | 2013-03-12 |
| 8372705 | Fabrication of CMOS transistors having differentially stressed spacers | Lahir Shaik Adam, Balasubramanian S. Haran, Bruce B. Doris | 2013-02-12 |
| 8232179 | Method to improve wet etch budget in FEOL integration | Jason E. Cummings, Lisa F. Edge, Balasubramanian S. Haran, David V. Horak, Hemanth Jagannathan | 2012-07-31 |
| 7948083 | Reliable BEOL integration process with direct CMP of porous SiCOH dielectric | Christos D. Dimitrakopoulos, Stephen M. Gates, Vincent J. McGahay | 2011-05-24 |
| 7855428 | Conductive liner at an interface between a shallow trench isolation structure and a buried oxide layer | Robert H. Dennard, Mark C. Hakey, David V. Horak | 2010-12-21 |
| 7838428 | Method of repairing process induced dielectric damage by the use of GCIB surface treatment using gas clusters of organic molecular species | Shyng-Tsong Chen, Nancy R. Klymko, Anita Madan, Steven E. Molis | 2010-11-23 |
| 7816253 | Surface treatment of inter-layer dielectric | Shyng-Tsong Chen, Qinghuang Lin, Kelly Malone, Terry A. Spooner, Chih-Chao Yang | 2010-10-19 |
| 7704854 | Method for fabricating semiconductor device having conductive liner for rad hard total dose immunity | Robert H. Dennard, Mark C. Hakey, David V. Horak | 2010-04-27 |
| 7517736 | Structure and method of chemically formed anchored metallic vias | Daniel C. Edelstein, John A. Fitzsimmons, Stephan Grunow, Henry A. Nye, III, David L. Rath | 2009-04-14 |
| 7485582 | Hardmask for improved reliability of silicon based dielectrics | Son V. Nguyen, Michael Lane, Stephen M. Gates, Xiao Hu Liu, Vincent J. McGahay +1 more | 2009-02-03 |
| 7335980 | Hardmask for reliability of silicon based dielectrics | Son V. Nguyen, Michael Lane, Stephen M. Gates, Xiao Hu Liu, Vincent J. McGahay +1 more | 2008-02-26 |
| 7294565 | Method of fabricating a wire bond pad with Ni/Au metallization | Lloyd Burrell, Charles R. Davis, Ronald D. Goldblatt, William Francis Landers | 2007-11-13 |
| 7253105 | Reliable BEOL integration process with direct CMP of porous SiCOH dielectric | Christos D. Dimitrakopoulos, Stephen M. Gates, Vincent J. McGahay | 2007-08-07 |