Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10930566 | Complementary metal oxide semiconductor replacement gate high-k metal gate devices with work function adjustments | Hemanth Jagannathan, Paul C. Jamison, Vamsi K. Paruchuri | 2021-02-23 |
| 10573565 | Complementary metal oxide semiconductor replacement gate high-k metal gate devices with work function adjustments | Hemanth Jagannathan, Paul C. Jamison, Vamsi K. Paruchuri | 2020-02-25 |
| 10312259 | Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of manufacturing same | Bruce B. Doris, Pouya Hashemi, Alexander Reznicek | 2019-06-04 |
| 10304746 | Complementary metal oxide semiconductor replacement gate high-K metal gate devices with work function adjustments | Hemanth Jagannathan, Paul C. Jamison, Vamsi K. Paruchuri | 2019-05-28 |
| 10139358 | Method for characterization of a layered structure | Gangadhara Raja Muthinti, Shariq Siddiqui | 2018-11-27 |
| 9502420 | Structure and method for highly strained germanium channel fins for high mobility pFINFETs | Stephen W. Bedell, Pranita Kerber, Qiqing C. Ouyang, Alexander Reznicek | 2016-11-22 |
| 9490161 | Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of manufacturing same | Bruce B. Doris, Pouya Hashemi, Alexander Reznicek | 2016-11-08 |
| 9490255 | Complementary metal oxide semiconductor replacement gate high-k metal gate devices with work function adjustments | Hemanth Jagannathan, Paul C. Jamison, Vamsi K. Paruchuri | 2016-11-08 |
| 9406679 | Integration of multiple threshold voltage devices for complementary metal oxide semiconductor using full metal gate | Hemanth Jagannathan, Balasubramanian S. Haran | 2016-08-02 |
| 9093558 | Integration of multiple threshold voltage devices for complementary metal oxide semiconductor using full metal gate | Hemanth Jagannathan, Balasubramanian S. Haran | 2015-07-28 |
| 9059314 | Structure and method to obtain EOT scaled dielectric stacks | Hemanth Jagannathan, Takashi Ando, Sufi Zafar, Changhwan Choi, Paul C. Jamison +2 more | 2015-06-16 |
| 9006816 | Memory device having multiple dielectric gate stacks and related methods | Prasanna Khare, Stephane Allegret-Maret, Nicolas Loubet, Qing Liu, Hemanth Jagannathan +2 more | 2015-04-14 |
| 8860123 | Memory device having multiple dielectric gate stacks with first and second dielectric layers and related methods | Prasanna Khare, Stephane Allegret-Maret, Nicolas Loubet, Qing Liu, Hemanth Jagannathan +2 more | 2014-10-14 |
| 8796128 | Dual metal fill and dual threshold voltage for replacement gate metal devices | Nathaniel Berliner, James J. Demarest, Balasubramanian S. Haran, Raymond J. Donohue | 2014-08-05 |
| 8679941 | Method to improve wet etch budget in FEOL integration | Jason E. Cummings, Balasubramanian S. Haran, David V. Horak, Hemanth Jagannathan, Sanjay C. Mehta | 2014-03-25 |
| 8309447 | Method for integrating multiple threshold voltage devices for CMOS | Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Hemanth Jagannathan, Ali Khakifirooz +1 more | 2012-11-13 |
| 8304836 | Structure and method to obtain EOT scaled dielectric stacks | Hemanth Jagannathan, Takashi Ando, Sufi Zafar, Changhwan Choi, Paul C. Jamison +2 more | 2012-11-06 |
| 8232179 | Method to improve wet etch budget in FEOL integration | Jason E. Cummings, Balasubramanian S. Haran, David V. Horak, Hemanth Jagannathan, Sanjay C. Mehta | 2012-07-31 |
| 8232607 | Borderless contact for replacement gate employing selective deposition | Balasubramanian S. Haran | 2012-07-31 |
| 7790628 | Method of forming high dielectric constant films using a plurality of oxidation sources | Robert D. Clark | 2010-09-07 |