Issued Patents All Time
Showing 101–125 of 183 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10553700 | Gate cut in RMG | Siva Kanakasabapathy, Andrew M. Greene | 2020-02-04 |
| 10553498 | Integrated circuit with replacement gate stacks and method of forming same | Siddarth A. Krishnan | 2020-02-04 |
| 10546787 | Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device | Vijay Narayanan, Terence B. Hook, Hemanth Jagannathan | 2020-01-28 |
| 10535517 | Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS | Choonghyun Lee, Gen Tsutsui, Dechao Guo | 2020-01-14 |
| 10529815 | Conformal replacement gate electrode for short channel devices | Takashi Ando, Masanobu Hatanaka, Vijay Narayanan, Yohei Ogawa, John Rozen | 2020-01-07 |
| 10529628 | Semiconductor device and method of forming the semiconductor device | Brent A. Anderson, Paul C. Jamison, Choonghyun Lee | 2020-01-07 |
| 10490559 | Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions | Takashi Ando, Pouya Hashemi, Choonghyun Lee | 2019-11-26 |
| 10468412 | Formation of a semiconductor device with selective nitride grown on conductor | Dechao Guo, Zuoguang Liu | 2019-11-05 |
| 10439043 | Formation of self-aligned bottom spacer for vertical transistors | Hemanth Jagannathan, Choonghyun Lee, Shogo Mochizuki | 2019-10-08 |
| 10418288 | Techniques for forming different gate length vertical transistors with dual gate oxide | Shogo Mochizuki, Choonghyun Lee, Chun Wing Yeung | 2019-09-17 |
| 10395989 | Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETs | Hemanth Jagannathan, Paul C. Jamison, Choonghyun Lee | 2019-08-27 |
| 10395988 | Vertical FET transistor with reduced source/drain contact resistance | Kangguo Cheng, Zheng Xu, Zhenxing Bi | 2019-08-27 |
| 10381479 | Interface charge reduction for SiGe surface | Devendra K. Sadana, Dechao Guo, Joel P. de Souza, Stephen W. Bedell, Shogo Mochizuki +3 more | 2019-08-13 |
| 10373912 | Replacement metal gate processes for vertical transport field-effect transistor | Choonghyun Lee, Chun Wing Yeung, Hemanth Jagannathan | 2019-08-06 |
| 10361132 | Structures with thinned dielectric material | Takashi Ando, Aritra Dasgupta, Kai Zhao, Unoh Kwon, Siddarth A. Krishnan | 2019-07-23 |
| 10361130 | Dual channel silicon/silicon germanium complementary metal oxide semiconductor performance with interface engineering | Hemanth Jagannathan, Choonghyun Lee, Richard Southwick | 2019-07-23 |
| 10354999 | Structure and method to suppress work function effect by patterning boundary proximity in replacement metal gate | Unoh Kwon, Kai Zhao | 2019-07-16 |
| 10340340 | Multiple-threshold nanosheet transistors | Michael A. Guillorn, Terence B. Hook, Nicolas Loubet, Robert R. Robison, Reinaldo Vega +1 more | 2019-07-02 |
| 10332883 | Integrated metal gate CMOS devices | Dechao Guo, Vijay Narayanan | 2019-06-25 |
| 10325815 | Vertical transport fin field effect transistors having different channel lengths | Choonghyun Lee, Shogo Mochizuki, Chun Wing Yeung | 2019-06-18 |
| 10312157 | Field effect transistor stack with tunable work function | Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan | 2019-06-04 |
| 10312147 | Multi-layer work function metal gates with similar gate thickness to achieve multi-VT for VFETs | Hemanth Jagannathan, Paul C. Jamison, Choonghyun Lee | 2019-06-04 |
| 10312237 | Vertical transport transistors with equal gate stack thicknesses | Zhenxing Bi, Choonghyun Lee, Zheng Xu | 2019-06-04 |
| 10297598 | Formation of full metal gate to suppress interficial layer growth | Hemanth Jagannathan, Paul C. Jamison, Choonghyun Lee, Vijay Narayanan | 2019-05-21 |
| 10297671 | Uniform threshold voltage for nanosheet devices | Hemanth Jagannathan, Paul C. Jamison, Choonghyun Lee, Vijay Narayanan, Koji Watanabe | 2019-05-21 |