Issued Patents All Time
Showing 151–175 of 183 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10068805 | Self-aligned spacer for cut-last transistor fabrication | Dechao Guo, Zuoguang Liu | 2018-09-04 |
| 10032856 | Nanosheet capacitor | Zhenxing Bi, Kangguo Cheng, Zheng Xu | 2018-07-24 |
| 10020378 | Self-aligned spacer for cut-last transistor fabrication | Dechao Guo, Zuoguang Liu | 2018-07-10 |
| 10020255 | Integration of super via structure in BEOL | Joe Lee, Yann Mignot, Hosadurga Shobha, Junli Wang, Yongan Xu | 2018-07-10 |
| 10020254 | Integration of super via structure in BEOL | Joe Lee, Yann Mignot, Hosadurga Shobha, Junli Wang, Yongan Xu | 2018-07-10 |
| 10008417 | Vertical transport fin field effect transistors having different channel lengths | Choonghyun Lee, Shogo Mochizuki, Chun Wing Yeung | 2018-06-26 |
| 10002937 | Shared metal gate stack with tunable work function | Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan | 2018-06-19 |
| 10002791 | Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETS | Hemanth Jagannathan, Paul C. Jamison, Choonghyun Lee | 2018-06-19 |
| 9997519 | Dual channel structures with multiple threshold voltages | Michael A. Guillorn, Vijay Narayanan | 2018-06-12 |
| 9997518 | Low resistive electrode for an extendable high-k metal gate stack | Keith Kwong Hon Wong | 2018-06-12 |
| 9960272 | Bottom contact resistance reduction on VFET | Choonghyun Lee, Shogo Mochizuki, Hemanth Jagannathan | 2018-05-01 |
| 9960161 | Low resistive electrode for an extendable high-k metal gate stack | Keith Kwong Hon Wong | 2018-05-01 |
| 9941282 | Integrated metal gate CMOS devices | Dechao Guo, Vijay Narayanan | 2018-04-10 |
| 9922884 | Integrated circuit with replacement gate stacks and method of forming same | Siddarth A. Krishnan | 2018-03-20 |
| 9922983 | Threshold voltage modulation through channel length adjustment | Dechao Guo, Derrick Liu, Huimei Zhou | 2018-03-20 |
| 9922984 | Threshold voltage modulation through channel length adjustment | Dechao Guo, Derrick Liu, Huimei Zhou | 2018-03-20 |
| 9917210 | FinFET transistor gate and epitaxy formation | Zhenxing Bi, Kangguo Cheng, Zheng Xu | 2018-03-13 |
| 9905476 | Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs | Siddarth A. Krishnan, Unoh Kwon, Keith Kwong Hon Wong | 2018-02-27 |
| 9899264 | Integrated metal gate CMOS devices | Dechao Guo, Vijay Narayanan | 2018-02-20 |
| 9859169 | Field effect transistor stack with tunable work function | Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan | 2018-01-02 |
| 9818746 | Structure and method to suppress work function effect by patterning boundary proximity in replacement metal gate | Unoh Kwon, Kai Zhao | 2017-11-14 |
| 9799656 | Semiconductor device having a gate stack with tunable work function | Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan | 2017-10-24 |
| 9768171 | Method to form dual tin layers as pFET work metal stack | Siddarth A. Krishnan | 2017-09-19 |
| 9704758 | Forming a semiconductor structure for reduced negative bias temperature instability | Siddarth A. Krishnan | 2017-07-11 |
| 9704754 | Self-aligned spacer for cut-last transistor fabrication | Dechao Guo, Zuoguang Liu | 2017-07-11 |