Issued Patents All Time
Showing 51–75 of 183 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11024711 | Nanosheet FET bottom isolation | Zhenxing Bi, Kangguo Cheng, Zheng Xu | 2021-06-01 |
| 11024369 | Static random-access memory cell design | Lan Yu, Junli Wang, Heng Wu, Dechao Guo | 2021-06-01 |
| 11011517 | Semiconductor structure including first FinFET devices for low power applications and second FinFET devices for high power applications | Lan Yu, Junli Wang, Heng Wu, Dechao Guo | 2021-05-18 |
| 11004850 | Vertical fin field effect transistor devices with a replacement metal gate | Junli Wang, Michael P. Belyansky | 2021-05-11 |
| 10985075 | Gate formation scheme for n-type and p-type transistors having separately tuned threshold voltages | Unoh Kwon, Vijay Narayanan | 2021-04-20 |
| 10971626 | Interface charge reduction for SiGe surface | Devendra K. Sadana, Dechao Guo, Joel P. de Souza, Stephen W. Bedell, Shogo Mochizuki +3 more | 2021-04-06 |
| 10971399 | Oxygen-free replacement liner for improved transistor performance | Heng Wu, Dechao Guo, Junli Wang | 2021-04-06 |
| 10957696 | Self-aligned metal gate with poly silicide for vertical transport field-effect transistors | Brent A. Anderson, Dechao Guo, Vijay Narayanan | 2021-03-23 |
| 10957646 | Hybrid BEOL metallization utilizing selective reflection mask | Benjamin D. Briggs, Cornelius Brown Peethala, Michael Rizzolo, Koichi Motoyama, Gen Tsutsui +2 more | 2021-03-23 |
| 10943989 | Gate to source/drain leakage reduction in nanosheet transistors via inner spacer optimization | Heng Wu, Junli Wang, Lan Yu, Dechao Guo | 2021-03-09 |
| 10937648 | Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS | Choonghyun Lee, Gen Tsutsui, Dechao Guo | 2021-03-02 |
| 10930734 | Nanosheet FET bottom isolation | Zhenxing Bi, Kangguo Cheng, Zheng Xu | 2021-02-23 |
| 10903418 | Low resistance electrode for high aspect ratio confined PCM cell in BEOL | Nicole Saulnier | 2021-01-26 |
| 10903124 | Transistor structure with n/p boundary buffer | Romain Lallement, Indira Seshadri | 2021-01-26 |
| 10892339 | Gate first technique in vertical transport FET using doped silicon gates with silicide | Hemanth Jagannathan, Paul C. Jamison, Choonghyun Lee, Sanjay C. Mehta, Vijay Narayanan | 2021-01-12 |
| 10833146 | Horizontal-trench capacitor | Zheng Xu, Zhenxing Bi, Dongbing Shao | 2020-11-10 |
| 10832975 | Reduced static random access memory (SRAM) device foot print through controlled bottom source/drain placement | Brent A. Anderson, Junli Wang, Kangguo Cheng, Choonghyun Lee, Hemanth Jagannathan | 2020-11-10 |
| 10804368 | Semiconductor device having two-part spacer | Junli Wang, Dechao Guo, Heng Wu, Ernest Y. Wu | 2020-10-13 |
| 10797163 | Leakage control for gate-all-around field-effect transistor devices | Lan Yu, Heng Wu, Junli Wang, Dechao Guo | 2020-10-06 |
| 10790199 | Dual channel silicon/silicon germanium complementary metal oxide semiconductor performance with interface engineering | Hemanth Jagannathan, Choonghyun Lee, Richard Southwick | 2020-09-29 |
| 10790271 | Perpendicular stacked field-effect transistor device | Zheng Xu, Chen Zhang, Dongbing Shao | 2020-09-29 |
| 10777469 | Self-aligned top spacers for vertical FETs with in situ solid state doping | Junli Wang, Brent A. Anderson, Xin Miao | 2020-09-15 |
| 10777659 | Self-aligned bottom source/drain epitaxial growth in vertical field effect transistors | Choonghyun Lee, Shogo Mochizuki, Brent A. Anderson, Hemanth Jagannathan | 2020-09-15 |
| 10756194 | Shared metal gate stack with tunable work function | Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan | 2020-08-25 |
| 10749012 | Formation of self-aligned bottom spacer for vertical transistors | Hemanth Jagannathan, Choonghyun Lee, Shogo Mochizuki | 2020-08-18 |