Issued Patents All Time
Showing 26–50 of 1,139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12402408 | Stacked FETS including devices with thick gate oxide | Julien Frougier, Nicolas Loubet, Junli Wang, Ruqiang Bao, Min Gyu Sung +2 more | 2025-08-26 |
| 12396227 | Full wrap around backside contact | Kisik Choi, Junli Wang, Julien Frougier, Min Gyu Sung | 2025-08-19 |
| 12396247 | Work function metal patterning for nanosheet CFETs | Chen Zhang, Kangguo Cheng, Juntao Li | 2025-08-19 |
| 12396225 | Method to release nano sheet after nano sheet fin recess | Chanro Park, Kangguo Cheng, Juntao Li, Choonghyun Lee | 2025-08-19 |
| 12394660 | Buried power rail after replacement metal gate | Devika Sarkar Grant, Sagarika Mukesh, Kisik Choi, Somnath Ghosh | 2025-08-19 |
| 12394462 | Stacked FET with three-terminal SOT MRAM | Pouya Hashemi | 2025-08-19 |
| 12389609 | Circuit architecture using transistors with dynamic dual functionality for logic and embedded memory drivers | Julien Frougier, Kangguo Cheng, Heng Wu, Min Gyu Sung, Chanro Park | 2025-08-12 |
| 12389813 | Resistive switching memory cell | Kangguo Cheng, Julien Frougier, Chanro Park | 2025-08-12 |
| 12382719 | Power gating dummy power transistors for back side power delivery networks | Tao Li, Kangguo Cheng | 2025-08-05 |
| 12382708 | Vertical stacked nanosheet CMOS transistors with different work function metals | Kangguo Cheng, Juntao Li, Chanro Park | 2025-08-05 |
| 12382682 | Gate-all-around nanosheet-FET with variable channel geometries for performance optimization | Julien Frougier, Heng Wu, Chen Zhang, Alexander Reznicek | 2025-08-05 |
| 12382665 | Increased gate length at given footprint for nanosheet device | Julien Frougier, Kangguo Cheng, Chanro Park | 2025-08-05 |
| 12382662 | Wrap-around-contact for 2D-channel gate-all-around field-effect-transistors | Julien Frougier, Kangguo Cheng, Chanro Park, Andrew Gaul | 2025-08-05 |
| 12363990 | Upper and lower gate configurations of monolithic stacked FinFET transistors | Chen Zhang, Junli Wang, Dechao Guo, Sung-Dae Suk | 2025-07-15 |
| 12363977 | Forming dielectric sidewall and bottom dielectric isolation in Fork-FET devices | Julien Frougier, Kangguo Cheng, Dimitri Houssameddine | 2025-07-15 |
| 12363965 | Stacked transistor layout for improved cell height scaling | Nicholas Anthony Lanzillo, Albert M. Chu, Daniel James Dechene, Eric Miller, Lawrence A. Clevenger | 2025-07-15 |
| 12362278 | Transistors with dual power and signal lines | Tao Li, David Wolpert, Albert M. Chu | 2025-07-15 |
| 12362004 | Scaled 2T DRAM | Min Gyu Sung, Julien Frougier, Chanro Park, Juntao Li | 2025-07-15 |
| 12356711 | Late gate extension | Christopher J. Waskiewicz, Jay William Strane, Hemanth Jagannathan, Brent A. Anderson | 2025-07-08 |
| 12356709 | Vertical field-effect transistor with isolation pillars | Brent A. Anderson | 2025-07-08 |
| 12356685 | Looped long channel field-effect transistor | Ardasheir Rahman, Hemanth Jagannathan, Robert R. Robison, Brent A. Anderson, Heng Wu | 2025-07-08 |
| 12356680 | Nanosheet device with air-gaped source/drain regions | Huimei Zhou, Yi Song, Kangguo Cheng | 2025-07-08 |
| 12349457 | Stacked transistors having bottom contact with replacement spacer | Kangguo Cheng, Julien Frougier, Heng Wu | 2025-07-01 |
| 12349406 | Hybrid gate cut for stacked transistors | Chen Zhang, Jingyun Zhang, Carl Radens | 2025-07-01 |
| 12347767 | Stacked FET contact formation | Koichi Motoyama, Jennifer Church, Oleg Gluschenkov | 2025-07-01 |