Issued Patents All Time
Showing 1,676–1,700 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9748336 | Semiconductor device including dual-layer source/drain region | Robert H. Dennard, Zhen Zhang | 2017-08-29 |
| 9741626 | Vertical transistor with uniform bottom spacer formed by selective oxidation | Nicolas Loubet, Xin Miao, Alexander Reznicek | 2017-08-22 |
| 9741792 | Bulk nanosheet with dielectric isolation | Bruce B. Doris, Junli Wang | 2017-08-22 |
| 9741722 | Dummy gate structure for electrical isolation of a fin DRAM | John E. Barth, Jr., Bruce B. Doris, Herbert L. Ho, Ali Khakifirooz, Babar A. Khan +4 more | 2017-08-22 |
| 9741717 | FinFETs with controllable and adjustable channel doping | Xin Miao, Wenyu Xu, Chen Zhang | 2017-08-22 |
| 9741716 | Forming vertical and horizontal field effect transistors on the same substrate | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2017-08-22 |
| 9741672 | Preventing unauthorized use of integrated circuits for radiation-hard applications | Bruce B. Doris, Ali Khakifirooz, Kenneth P. Rodbell | 2017-08-22 |
| 9741609 | Middle of line cobalt interconnection | Lawrence A. Clevenger, Balasubramanian S. Pranatharthi Haran, John H. Zhang | 2017-08-22 |
| 9735162 | Dynamic random access memory cell with self-aligned strap | John E. Barth, Jr., Herbert L. Ho, Ali Khakifirooz, Ravikumar Ramachandran, Kern Rim +1 more | 2017-08-15 |
| 9735277 | Partially dielectric isolated fin-shaped field effect transistor (FinFET) | Ramachandra Divakaruni, Johnathan E. Faltermeier, Edward J. Nowak, Kern Rim | 2017-08-15 |
| 9735272 | Method to controllably etch silicon recess for ultra shallow junctions | Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2017-08-15 |
| 9735269 | Integrated strained stacked nanosheet FET | Ramachandra Divakaruni, Juntao Li, Xin Miao | 2017-08-15 |
| 9735257 | finFET having highly doped source and drain regions | Ali Khakifirooz, Alexander Reznicek, Dominic J. Schepis | 2017-08-15 |
| 9735253 | Closely packed vertical transistors with reduced contact resistance | Zhenxing Bi, Juntao Li, Peng Xu | 2017-08-15 |
| 9735246 | Air-gap top spacer and self-aligned metal gate for vertical fets | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2017-08-15 |
| 9735234 | Stacked nanowire devices | Ramachandra Divakaruni, Juntao Li | 2017-08-15 |
| 9735176 | Stacked nanowires with multi-threshold voltage solution for PFETS | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-08-15 |
| 9735173 | Reduced parasitic capacitance and contact resistance in extremely thin silicon-on-insulator (ETSOI) devices due to wrap-around structure of source/drain regions | Ramachandra Divakaruni | 2017-08-15 |
| 9735160 | Method of co-integration of strained silicon and strained germanium in semiconductor devices including fin structures | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2017-08-15 |
| 9735155 | Bulk silicon germanium FinFET | Juntao Li, Shogo Mochizuki | 2017-08-15 |
| 9733210 | Nanofluid sensor with real-time spatial sensing | Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi | 2017-08-15 |
| 9728625 | Fin formation in fin field effect transistors | Bruce B. Doris, Hong He, Ali Khakifirooz, Yunpeng Yin | 2017-08-08 |
| 9728622 | Dummy gate formation using spacer pull down hardmask | Marc A. Bergendahl, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan | 2017-08-08 |
| 9728621 | iFinFET | Juntao Li, Geng Wang, Qintao Zhang | 2017-08-08 |
| 9728649 | Semiconductor device including embedded crystalline back-gate bias planes, related design structure and method of fabrication | Thomas N. Adam, Ali Khakifirooz, Alexander Reznicek, Raghavasimhan Sreenivasan | 2017-08-08 |