Issued Patents All Time
Showing 1,701–1,725 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9728635 | Uniform gate length in vertical field effect transistors | Peng Xu | 2017-08-08 |
| 9728626 | Almost defect-free active channel region | Dominic J. Schepis, Charan V. Surisetty, Alexander Reznicek | 2017-08-08 |
| 9721897 | Transistor with air spacer and self-aligned contact | Xin Miao, Peng Xu, Chen Zhang | 2017-08-01 |
| 9721845 | Vertical field effect transistors with bottom contact metal directly beneath fins | Xin Miao, Wenyu Xu, Chen Zhang | 2017-08-01 |
| 9721885 | Electrical fuse and/or resistor structures | Veeraraghavan S. Basker, Ali Khakifirooz, Juntao Li | 2017-08-01 |
| 9721848 | Cutting fins and gates in CMOS devices | Huiming Bu, Andrew M. Greene, Dechao Guo, Sivananda K. Kanakasabapathy, Gauri Karve +6 more | 2017-08-01 |
| 9721851 | Silicon-germanium fin formation | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2017-08-01 |
| 9722125 | Radiation sensor, method of forming the sensor and device including the sensor | Xin Miao, Wenyu Xu, Chen Zhang | 2017-08-01 |
| 9722052 | Fin cut without residual fin defects | Pouya Hashemi, Alexander Reznicek, Dominic J. Schepis | 2017-08-01 |
| 9722048 | Vertical transistors with reduced bottom electrode series resistance | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-08-01 |
| 9722043 | Self-aligned trench silicide process for preventing gate contact to silicide shorts | Veeraraghavan S. Basker | 2017-08-01 |
| 9721970 | Gate all-around FinFET device and a method of manufacturing same | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-08-01 |
| 9716158 | Air gap spacer between contact and gate region | Nicolas Loubet, Xin Miao, Alexander Reznicek | 2017-07-25 |
| 9716184 | Enabling large feature alignment marks with sidewall image transfer patterning | Sivananda K. Kanakasabapathy, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre +1 more | 2017-07-25 |
| 9716170 | Reduced capacitance in vertical transistors by preventing excessive overlap between the gate and the source/drain | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2017-07-25 |
| 9716155 | Vertical field-effect-transistors having multiple threshold voltages | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-07-25 |
| 9716145 | Strained stacked nanowire field-effect transistors (FETs) | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-07-25 |
| 9716142 | Stacked nanowires | Zhenxing Bi, Juntao Li, Xin Miao | 2017-07-25 |
| 9716086 | Method and structure for forming buried ESD with FinFETs | Nicolas Loubet, Xin Miao, Alexander Reznicek | 2017-07-25 |
| 9716064 | Electrical fuse and/or resistor structures | Veeraraghavan S. Basker, Ali Khakifirooz, Juntao Li | 2017-07-25 |
| 9716046 | Method and structure for forming dielectric isolated finFET with improved source/drain epitaxy | Juntao Li | 2017-07-25 |
| 9716045 | Directly forming SiGe fins on oxide | Hong He, Juntao Li, Junli Wang | 2017-07-25 |
| 9716042 | Fin field-effect transistor (FinFET) with reduced parasitic capacitance | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2017-07-25 |
| 9711618 | Fabrication of vertical field effect transistor structure with controlled gate length | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2017-07-18 |
| 9704994 | Different shallow trench isolation fill in fin and non-fin regions of finFET | Peng Xu, Chen Zhang | 2017-07-11 |