Issued Patents All Time
Showing 1,751–1,775 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9685532 | Replacement metal gate structures | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2017-06-20 |
| 9685510 | SiGe CMOS with tensely strained NFET and compressively strained PFET | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-06-20 |
| 9685507 | FinFET devices | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2017-06-20 |
| 9685499 | Nanosheet capacitor | Zhenxing Bi, Dongbing Shao, Zheng Xu | 2017-06-20 |
| 9685440 | Forming fins utilizing alternating pattern of spacers | Peng Xu | 2017-06-20 |
| 9685417 | Self-destructive circuits under radiation | Qing Cao, Fei Liu | 2017-06-20 |
| 9685409 | Top metal contact for vertical transistor structures | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-06-20 |
| 9679897 | High density nanofluidic structure with precisely controlled nano-channel dimensions | Qing Cao, Zhengwen Li, Fei Liu | 2017-06-13 |
| 9680116 | Carbon nanotube vacuum transistors | Qing Cao, Zhengwen Li, Fei Liu | 2017-06-13 |
| 9680015 | Dual epitaxy CMOS processing using selective nitride formation for reduced gate pitch | Ali Khakifirooz, Richard S. Wise | 2017-06-13 |
| 9679763 | Silicon-on-insulator fin field-effect transistor device formed on a bulk substrate | Pouya Hashemi, Alexander Reznicek, Dominic J. Schepis | 2017-06-13 |
| 9673196 | Field effect transistors with varying threshold voltages | Thomas N. Adam, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek | 2017-06-06 |
| 9673190 | ESD device compatible with bulk bias capability | Bruce B. Doris, Terence B. Hook, Ali Khakifirooz, Pranita Kerber, Balasubramanian Pranatharthiharan +1 more | 2017-06-06 |
| 9673222 | Fin isolation structures facilitating different fin isolation schemes | Ajey Poovannummoottil Jacob, Bruce B. Doris, Nicolas Loubet, Prasanna Khare, Rama Divakaruni | 2017-06-06 |
| 9673293 | Airgap spacers | Zuoguang Liu, Chun Wing Yeung | 2017-06-06 |
| 9673296 | Semiconductor structure having a source and a drain with reverse facets | Thomas N. Adam, Ali Khakifirooz, Jinghong Li, Alexander Reznicek | 2017-06-06 |
| 9673083 | Methods of forming fin isolation regions on FinFET semiconductor devices by implantation of an oxidation-retarding material | Ajey Poovannummoottil Jacob, Bruce B. Doris, Ali Khakifirooz, Kern Rim | 2017-06-06 |
| 9666267 | Structure and method for adjusting threshold voltage of the array of transistors | Jin Cai, Robert H. Dennard, Ali Khakifirooz, Tak H. Ning | 2017-05-30 |
| 9666533 | Airgap formation between source/drain contacts and gates | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2017-05-30 |
| 9666489 | Stacked nanowire semiconductor device | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-05-30 |
| 9659785 | Fin cut for taper device | Ruilong Xie, Tenko Yamashita | 2017-05-23 |
| 9659779 | Method and structure for enabling high aspect ratio sacrificial gates | Ryan O. Jung, Fee Li Lie, Jeffrey C. Shearer, John R. Sporre, Sean Teehan | 2017-05-23 |
| 9660032 | Method and apparatus providing improved thermal conductivity of strain relaxed buffer | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-05-23 |
| 9659963 | Contact formation to 3D monolithic stacked FinFETs | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2017-05-23 |
| 9659960 | Extremely thin silicon-on-insulator silicon germanium device without edge strain relaxation | Juntao Li, Zuoguang Liu, Xin Miao | 2017-05-23 |