Issued Patents All Time
Showing 1,801–1,825 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9647123 | Self-aligned sigma extension regions for vertical transistors | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-05-09 |
| 9647120 | Vertical FET symmetric and asymmetric source/drain formation | Zhenxing Bi, Juntao Li, Peng Xu | 2017-05-09 |
| 9647113 | Strained FinFET by epitaxial stressor independent of gate pitch | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek, Charan V. Surisetty | 2017-05-09 |
| 9640436 | MOSFET with asymmetric self-aligned contact | Xin Miao, Ruilong Xie, Tenko Yamashita | 2017-05-02 |
| 9640667 | III-V vertical field effect transistors with tunable bandgap source/drain regions | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-05-02 |
| 9633911 | Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs | Bruce B. Doris, Ali Khakifirooz, Qing Liu, Nicolas Loubet, Scott Luning | 2017-04-25 |
| 9633906 | Gate structure cut after formation of epitaxial active regions | Xiuyu Cai, Johnathan E. Faltermeier, Ali Khakifirooz, Theodorus E. Standaert, Ruilong Xie | 2017-04-25 |
| 9634142 | Method for improving boron diffusion in a germanium-rich fin through germanium concentration reduction in fin S/D regions by thermal mixing | Dominic J. Schepis, Alexander Reznicek, Pouya Hashemi | 2017-04-25 |
| 9634005 | Gate planarity for FinFET using dummy polish stop | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2017-04-25 |
| 9634004 | Forming reliable contacts on tight semiconductor pitch | Xiuyu Cai, Ali Khakifirooz, Ruilong Xie, Tenko Yamashita | 2017-04-25 |
| 9633943 | Method and structure for forming on-chip anti-fuse with reduced breakdown voltage | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2017-04-25 |
| 9633912 | Complementary heterogeneous MOSFET using global SiGe substrate and hard-mask memorized germanium dilution for nFET | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-04-25 |
| 9633908 | Method for forming a semiconductor structure containing high mobility semiconductor channel materials | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2017-04-25 |
| 9627382 | CMOS NFET and PFET comparable spacer width | Injo Ok, Soon-Cheon Seo | 2017-04-18 |
| 9627536 | Field effect transistors with strained channel features | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-04-18 |
| 9627511 | Vertical transistor having uniform bottom spacers | Juntao Li, Geng Wang, Qintao Zhang | 2017-04-18 |
| 9627491 | Aspect ratio trapping and lattice engineering for III/V semiconductors | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2017-04-18 |
| 9627381 | Confined N-well for SiGe strain relaxed buffer structures | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-04-18 |
| 9627377 | Self-aligned dielectric isolation for FinFET devices | Marc A. Bergendahl, David V. Horak, Ali Khakifirooz, Shom Ponoth, Theodorus E. Standaert +4 more | 2017-04-18 |
| 9627373 | CMOS compatible fuse or resistor using self-aligned contacts | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2017-04-18 |
| 9627278 | Method of source/drain height control in dual epi finFET formation | Veeraraghavan S. Basker, Ali Khakifirooz | 2017-04-18 |
| 9627277 | Method and structure for enabling controlled spacer RIE | Ryan O. Jung, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre +1 more | 2017-04-18 |
| 9627270 | Dual work function integration for stacked FinFET | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2017-04-18 |
| 9627267 | Integrated circuit having strained fins on bulk substrate and method to fabricate same | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-04-18 |
| 9627245 | Methods of forming alternative channel materials on a non-planar semiconductor device and the resulting device | Ajey Poovannummoottil Jacob, Bruce B. Doris, Nicolas Loubet | 2017-04-18 |