Issued Patents All Time
Showing 51–75 of 437 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11710666 | Dummy fin template to form a self-aligned metal contact for output of vertical transport field effect transistor | Brent A. Anderson, Albert M. Young | 2023-07-25 |
| 11710521 | Static random-access memory cell design | Lan Yu, Heng Wu, Ruqiang Bao, Dechao Guo | 2023-07-25 |
| 11695038 | Forming single and double diffusion breaks for fin field-effect transistor structures | Juntao Li, Kangguo Cheng, Ruilong Xie | 2023-07-04 |
| 11688635 | Oxygen-free replacement liner for improved transistor performance | Heng Wu, Dechao Guo, Ruqiang Bao | 2023-06-27 |
| 11670580 | Subtractive via etch for MIMCAP | Yann Mignot, Hsueh-Chung Chen, Mary Claire Silvestre, Chi-Chun Liu | 2023-06-06 |
| 11665877 | Stacked FET SRAM design | Chen Zhang, Ruilong Xie, Dechao Guo | 2023-05-30 |
| 11664455 | Wrap-around bottom contact for bottom source/drain | Alexander Reznicek, Ruilong Xie, Bruce B. Doris | 2023-05-30 |
| 11658116 | Interconnects on multiple sides of a semiconductor structure | Albert M. Chu, Dechao Guo, Brent A. Anderson | 2023-05-23 |
| 11621189 | Barrier-less prefilled via formation | Nicholas Anthony Lanzillo, Hosadurga Shobha, Lawrence A. Clevenger, Christopher J. Penny, Robert R. Robison +1 more | 2023-04-04 |
| 11621332 | Wraparound contact to a buried power rail | Ruilong Xie, Veeraraghavan S. Basker, Alexander Reznicek | 2023-04-04 |
| 11615988 | FinFET devices | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2023-03-28 |
| 11521927 | Buried power rail for scaled vertical transport field effect transistor | Ruilong Xie, Choonghyun Lee, Alexander Reznicek | 2022-12-06 |
| 11520768 | Vertical transistor and method of forming the vertical transistor | Fee Li Lie, Shogo Mochizuki | 2022-12-06 |
| 11489111 | Reversible resistive memory logic gate device | Hsueh-Chung Chen, Su Chen Fan | 2022-11-01 |
| 11456354 | Bulk nanosheet with dielectric isolation | Kangguo Cheng, Bruce B. Doris | 2022-09-27 |
| 11456219 | Gate-all-around FETs having uniform threshold voltage | Ruqiang Bao, Dechao Guo, Heng Wu | 2022-09-27 |
| 11380842 | Phase change memory cell with second conductive layer | Juntao Li, Kangguo Cheng, Ruilong Xie | 2022-07-05 |
| 11355401 | Field effect transistor | Effendi Leobandung, Veeraraghavan S. Basker, Albert M. Chu | 2022-06-07 |
| 11348999 | Nanosheet semiconductor devices with sigma shaped inner spacer | Alexander Reznicek, Chun-Chen Yeh, Veeraraghavan S. Basker | 2022-05-31 |
| 11289573 | Contact resistance reduction in nanosheet device structure | Heng Wu, Dechao Guo, Ruqiang Bao, Lan Yu, Reinaldo Vega +1 more | 2022-03-29 |
| 11282838 | Stacked gate structures | Chen Zhang, Dechao Guo, Ruilong Xie, Kangguo Cheng, Juntao Li +5 more | 2022-03-22 |
| 11276576 | Gate metal patterning to avoid gate stack attack due to excessive wet etching | Alexander Reznicek, Shogo Mochizuki, Joshua M. Rubin | 2022-03-15 |
| 11251304 | Wrap-around bottom contact for bottom source/drain | Alexander Reznicek, Ruilong Xie, Bruce B. Doris | 2022-02-15 |
| 11251179 | Long channel and short channel vertical FET co-integration for vertical FET VTFET | Terence B. Hook, Baozhen Li, Kirk D. Peterson | 2022-02-15 |
| 11239360 | Vertical transport field effect transistor structure with self-aligned top junction through early top source/drain epitaxy | Shogo Mochizuki, Brent A. Anderson, Hemanth Jagannathan | 2022-02-01 |