Issued Patents All Time
Showing 126–150 of 225 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10020359 | Leakage current reduction in stacked metal-insulator-metal capacitors | Takashi Ando, Paul C. Jamison, John Rozen | 2018-07-10 |
| 10008386 | Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device | Takashi Ando, Pouya Hashemi, Choonghyun Lee, Vijay Narayanan | 2018-06-26 |
| 10002791 | Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETS | Ruqiang Bao, Paul C. Jamison, Choonghyun Lee | 2018-06-19 |
| 9984263 | Simplified gate stack process to improve dual channel CMOS performance | Choonghyun Lee, Richard Southwick | 2018-05-29 |
| 9978748 | Method of cutting fins to create diffusion breaks for finFETs | Sivananda K. Kanakasabapathy, Alexander Reznicek | 2018-05-22 |
| 9960272 | Bottom contact resistance reduction on VFET | Ruqiang Bao, Choonghyun Lee, Shogo Mochizuki | 2018-05-01 |
| 9954106 | III-V fin on insulator | Kangguo Cheng, Alexander Reznicek | 2018-04-24 |
| 9941371 | Selective thickening of pFET dielectric | Takashi Ando, Barry P. Linder | 2018-04-10 |
| 9917089 | III-V semiconductor CMOS FinFET device | Alexander Reznicek, Devendra K. Sadana, Charan V. Surisetty | 2018-03-13 |
| 9881797 | Replacement gate electrode with multi-thickness conductive metallic nitride layers | Vamsi K. Paruchuri | 2018-01-30 |
| 9876091 | Divot-free planarization dielectric layer for replacement gate | Sanjay C. Mehta | 2018-01-23 |
| 9865730 | VTFET devices utilizing low temperature selective epitaxy | Shogo Mochizuki | 2018-01-09 |
| 9865703 | High-K layer chamfering to prevent oxygen ingress in replacement metal gate (RMG) process | Takashi Ando, Veeraraghavan S. Basker, Johnathan E. Faltermeier, Tenko Yamashita | 2018-01-09 |
| 9837357 | Method to reduce variability in contact resistance | Praneet Adusumilli, Christian Lavoie, Jean L. Sweet | 2017-12-05 |
| 9824930 | Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme | Takashi Ando, Balaji Kannan, Siddarth A. Krishnan, Unoh Kwon, Rekha Rajaram | 2017-11-21 |
| 9818616 | Controlling threshold voltage in nanosheet transistors | Paul C. Jamison | 2017-11-14 |
| 9773875 | Fabrication of silicon-germanium fin structure having silicon-rich outer surface | Choonghyun Lee, Shogo Mochizuki, Koji Watanabe | 2017-09-26 |
| 9761722 | Isolation of bulk FET devices with embedded stressors | Nicolas Loubet | 2017-09-12 |
| 9761655 | Stacked planar capacitors with scaled EOT | Takashi Ando, Lawrence A. Clevenger, Roger A. Quon | 2017-09-12 |
| 9754967 | Structure for integration of an III-V compound semiconductor on SOI | Alexander Reznicek | 2017-09-05 |
| 9741812 | Dual metal interconnect structure | Praneet Adusumilli, Koichi Motoyama, Oscar van der Straten | 2017-08-22 |
| 9741822 | Simplified gate stack process to improve dual channel CMOS performance | Choonghyun Lee, Richard Southwick | 2017-08-22 |
| 9721842 | Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme | Takashi Ando, Balaji Kannan, Siddarth A. Krishnan, Unoh Kwon, Rekha Rajaram | 2017-08-01 |
| 9722038 | Metal cap protection layer for gate and contact metallization | Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang | 2017-08-01 |
| 9666486 | Contained punch through stopper for CMOS structures on a strain relaxed buffer substrate | Mona A. Ebrish, Shogo Mochizuki, Alexander Reznicek | 2017-05-30 |