Issued Patents All Time
Showing 76–100 of 225 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10559672 | Vertical transport field-effect transistor including dual layer top spacer | Choonghyun Lee, Alexander Reznicek, Christopher J. Waskiewicz | 2020-02-11 |
| 10559671 | Vertical transport field-effect transistor including air-gap top spacer | Choonghyun Lee, Alexander Reznicek, Christopher J. Waskiewicz | 2020-02-11 |
| 10546787 | Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device | Ruqiang Bao, Vijay Narayanan, Terence B. Hook | 2020-01-28 |
| 10541239 | Semiconductor device and method of forming the semiconductor device | Robin Hsin Kuo Chao, Choonghyun Lee, Chun Wing Yeung, Jingyun Zhang | 2020-01-21 |
| 10535773 | FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation | Dechao Guo, Shogo Mochizuki, Gen Tsutsui, Chun-Chen Yeh | 2020-01-14 |
| 10529573 | Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device | Takashi Ando, Pouya Hashemi, Choonghyun Lee, Vijay Narayanan | 2020-01-07 |
| 10504997 | Silicon-germanium Fin structure having silicon-rich outer surface | Choonghyun Lee, Shogo Mochizuki, Koji Watanabe | 2019-12-10 |
| 10483361 | Wrap-around-contact structure for top source/drain in vertical FETs | Choonghyun Lee, Christopher J. Waskiewicz, Alexander Reznicek | 2019-11-19 |
| 10461172 | Vertical transistors having improved gate length control using uniformly deposited spacers | Christopher J. Waskiewicz, Yann Mignot, Stuart A. Sieg | 2019-10-29 |
| 10439043 | Formation of self-aligned bottom spacer for vertical transistors | Ruqiang Bao, Choonghyun Lee, Shogo Mochizuki | 2019-10-08 |
| 10431502 | Maskless epitaxial growth of phosphorus-doped Si and boron-doped SiGe (Ge) for advanced source/drain contact | Choonghyun Lee, Shogo Mochizuki, Chun Wing Yeung | 2019-10-01 |
| 10396076 | Structure and method for multiple threshold voltage definition in advanced CMOS device technology | Vijay Narayanan | 2019-08-27 |
| 10395080 | Simplified gate stack process to improve dual channel CMOS performance | Choonghyun Lee, Richard Southwick | 2019-08-27 |
| 10396146 | Leakage current reduction in stacked metal-insulator-metal capacitors | Takashi Ando, Paul C. Jamison, John Rozen | 2019-08-27 |
| 10395079 | Simplified gate stack process to improve dual channel CMOS performance | Choonghyun Lee, Richard Southwick | 2019-08-27 |
| 10395989 | Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETs | Ruqiang Bao, Paul C. Jamison, Choonghyun Lee | 2019-08-27 |
| 10381433 | Leakage current reduction in stacked metal-insulator-metal capacitors | Takashi Ando, Paul C. Jamison, John Rozen | 2019-08-13 |
| 10381479 | Interface charge reduction for SiGe surface | Devendra K. Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen W. Bedell +3 more | 2019-08-13 |
| 10373912 | Replacement metal gate processes for vertical transport field-effect transistor | Choonghyun Lee, Chun Wing Yeung, Ruqiang Bao | 2019-08-06 |
| 10361129 | Self-aligned double patterning formed fincut | Stuart A. Sieg, Yann Mignot, Christopher J. Waskiewicz, Eric R. Miller, Indira Seshadri | 2019-07-23 |
| 10361130 | Dual channel silicon/silicon germanium complementary metal oxide semiconductor performance with interface engineering | Ruqiang Bao, Choonghyun Lee, Richard Southwick | 2019-07-23 |
| 10340355 | Method of forming a dual metal interconnect structure | Praneet Adusumilli, Koichi Motoyama, Oscar van der Straten | 2019-07-02 |
| 10319833 | Vertical transport field-effect transistor including air-gap top spacer | Choonghyun Lee, Alexander Reznicek, Christopher J. Waskiewicz | 2019-06-11 |
| 10312147 | Multi-layer work function metal gates with similar gate thickness to achieve multi-VT for VFETs | Ruqiang Bao, Paul C. Jamison, Choonghyun Lee | 2019-06-04 |
| 10304938 | Maskless method to reduce source-drain contact resistance in CMOS devices | Praneet Adusumilli, Christian Lavoie | 2019-05-28 |