Issued Patents All Time
Showing 201–225 of 304 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10269812 | Forming contacts for VFETs | Ruilong Xie, Lars Liebmann, Daniel Chanemougame, John H. Zhang, Steven Bentley +1 more | 2019-04-23 |
| 10249726 | Methods of forming a protection layer on a semiconductor device and the resulting device | Ruilong Xie, Xiuyu Cai | 2019-04-02 |
| 10243053 | Gate contact structure positioned above an active region of a transistor device | Ruilong Xie, Andre P. Labonte | 2019-03-26 |
| 10236291 | Methods, apparatus and system for STI recess control for highly scaled finFET devices | Min Gyu Sung, Hoon Kim, Ruilong Xie, Kwan-Yong Lim | 2019-03-19 |
| 10229855 | Methods of forming transistor devices with different threshold voltages and the resulting devices | Hoon Kim, Ruilong Xie, Min Gyu Sung | 2019-03-12 |
| 10217846 | Vertical field effect transistor formation with critical dimension control | Ruilong Xie, Steven Bentley, Min Gyu Sung, Steven R. Soss, Hui Zang +8 more | 2019-02-26 |
| 10217839 | Field effect transistor (FET) with a gate having a recessed work function metal layer and method of forming the FET | Kisup Chung, Victor Chan, Koji Watanabe | 2019-02-26 |
| 10211147 | Metal-insulator-metal capacitors with dielectric inner spacers | Xunyuan Zhang, Lei Sun, Yi Qi, Roderick A. Augur | 2019-02-19 |
| 10211092 | Transistor with robust air spacer | Kangguo Cheng | 2019-02-19 |
| 10211100 | Methods of forming an air gap adjacent a gate of a transistor and a gate contact above the active region of the transistor | Ruilong Xie, Lars Liebmann, Nigel G. Cave, Andre P. Labonte, Nicholas V. LiCausi +1 more | 2019-02-19 |
| 10204994 | Methods of forming a semiconductor device with a gate contact positioned above the active region | Ruilong Xie, Andre P. Labonte, Lars Liebmann, Nigel G. Cave, Mark V. Raymond +2 more | 2019-02-12 |
| 10177241 | Methods of forming a gate contact for a transistor above the active region and an air gap adjacent the gate of the transistor | Ruilong Xie, Hoon Kim, Min Gyu Sung | 2019-01-08 |
| 10176996 | Replacement metal gate and fabrication process with reduced lithography steps | Min Gyu Sung, Hoon Kim | 2019-01-08 |
| 10177041 | Fin-type field effect transistors (FINFETS) with replacement metal gates and methods | Ruilong Xie, Laertis Economikos, Min Gyu Sung | 2019-01-08 |
| 10157796 | Forming of marking trenches in structure for multiple patterning lithography | Laertis Economikos, Ruilong Xie, Pei Liu | 2018-12-18 |
| 10121702 | Methods, apparatus and system for forming source/drain contacts using early trench silicide cut | Min Gyu Sung, Ruilong Xie, Puneet Harischandra Suvarna | 2018-11-06 |
| 10115629 | Air gap spacer formation for nano-scale semiconductor devices | Kangguo Cheng, Thomas J. Haigh, Jr., Juntao Li, Eric G. Liniger, Sanjay C. Mehta +2 more | 2018-10-30 |
| 10103238 | Nanosheet field-effect transistor with full dielectric isolation | Hui Zang, Tek Po Rinus Lee, Haigou Huang, Ruilong Xie, Min Gyu Sung | 2018-10-16 |
| 10090402 | Methods of forming field effect transistors (FETS) with gate cut isolation regions between replacement metal gates | Chang Ho Maeng, Pei Liu, Junsic Hong, Laertis Economikos, Ruilong Xie | 2018-10-02 |
| 10084053 | Gate cuts after metal gate formation | Ruilong Xie, Min Gyu Sung | 2018-09-25 |
| 10050118 | Semiconductor device configured for avoiding electrical shorting | Ruilong Xie, Ryan Ryoung-Han Kim, William J. Taylor, Jr., John A. Iacoponi | 2018-08-14 |
| 10038065 | Method of forming a semiconductor device with a gate contact positioned above the active region | Ruilong Xie, Min Gyu Sung, Hoon Kim | 2018-07-31 |
| 10026655 | Dual liner CMOS integration methods for FinFET devices | Min Gyu Sung, Ruilong Xie, Hoon Kim | 2018-07-17 |
| 10014209 | Methods, apparatus and system for local isolation formation for finFET devices | Min Gyu Sung, Ruilong Xie, Hoon Kim, Sukwon Hong | 2018-07-03 |
| 10014389 | Methods of forming IC products comprising a nano-sheet device and a transistor device having first and second replacement gate structures | Ruilong Xie, Min Gyu Sung, Hoon Kim | 2018-07-03 |