Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10886178 | Device with highly active acceptor doping and method of production thereof | Annie Levesque, Qun Gao, Hui Zang, Rishikesh Krishnan, Bharat Krishnan +1 more | 2021-01-05 |
| 10872979 | Spacer structures for a transistor device | Hui Zang, Chung Foong Tan, Guowei Xu, Haiting Wang, Yue Zhong +2 more | 2020-12-22 |
| 10629739 | Methods of forming spacers adjacent gate structures of a transistor device | Hui Zang, Chung Foong Tan, Guowei Xu, Haiting Wang, Yue Zhong +2 more | 2020-04-21 |
| 10276683 | Common metal contact regions having different Schottky barrier heights and methods of manufacturing same | Jinping Liu, Ruilong Xie | 2019-04-30 |
| 10263122 | Methods, apparatus, and manufacturing system for self-aligned patterning of contacts in a vertical field effect transistor | Hui Zang, Ruilong Xie, Lars Liebmann | 2019-04-16 |
| 10242982 | Method for forming a protection device having an inner contact spacer and the resulting devices | Ruilong Xie, Katsunori Onishi | 2019-03-26 |
| 10230000 | Vertical-transport transistors with self-aligned contacts | Emilie Bourjot, Daniel Chanemougame, Ruilong Xie, Hui Zang | 2019-03-12 |
| 10170544 | Integrated circuit products that include FinFET devices and a protection layer formed on an isolation region | Ruilong Xie, Christopher M. Prindle, Min Gyu Sung | 2019-01-01 |
| 10109714 | Buried contact structures for a vertical field-effect transistor | Hui Zang | 2018-10-23 |
| 10103238 | Nanosheet field-effect transistor with full dielectric isolation | Hui Zang, Haigou Huang, Ruilong Xie, Min Gyu Sung, Chanro Park | 2018-10-16 |
| 9876077 | Methods of forming a protection layer on an isolation region of IC products comprising FinFET devices | Ruilong Xie, Christopher M. Prindle, Min Gyu Sung | 2018-01-23 |
| 9831317 | Buried contact structures for a vertical field-effect transistor | Hui Zang | 2017-11-28 |
| 9812543 | Common metal contact regions having different Schottky barrier heights and methods of manufacturing same | Jinping Liu, Ruilong Xie | 2017-11-07 |
| 9570552 | Forming symmetrical stress liners for strained CMOS vertical nanowire field-effect transistors | Jinping Liu | 2017-02-14 |