Issued Patents All Time
Showing 251–275 of 304 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9735061 | Methods to form multi threshold-voltage dual channel without channel doping | Hoon Kim, Min Gyu Sung, Ruilong Xie | 2017-08-15 |
| 9735242 | Semiconductor device with a gate contact positioned above the active region | Ruilong Xie, Min Gyu Sung, Hoon Kim | 2017-08-15 |
| 9735060 | Hybrid fin cut etching processes for products comprising tapered and non-tapered FinFET semiconductor devices | Min Gyu Sung, Ruilong Xie, Hoon Kim | 2017-08-15 |
| 9735063 | Methods for forming fin structures | Min Gyu Sung, Hoon Kim, Ruilong Xie | 2017-08-15 |
| 9722053 | Methods, apparatus and system for local isolation formation for finFET devices | Min Gyu Sung, Ruilong Xie, Hoon Kim, Sukwon Hong | 2017-08-01 |
| 9691664 | Dual thick EG oxide integration under aggressive SG fin pitch | Min Gyu Sung, Hoon Kim, Ruilong Xie | 2017-06-27 |
| 9685522 | Forming uniform WF metal layers in gate areas of nano-sheet structures | Hoon Kim, Min Gyu Sung, Ruilong Xie | 2017-06-20 |
| 9653356 | Methods of forming self-aligned device level contact structures | Ruilong Xie, Min Gyu Sung, Hoon Kim | 2017-05-16 |
| 9646884 | Block level patterning process | Sukwon Hong, Hoon Kim, Min Gyu Sung | 2017-05-09 |
| 9634115 | Methods of forming a protection layer on a semiconductor device and the resulting device | Ruilong Xie, Xiuyu Cai | 2017-04-25 |
| 9627535 | Semiconductor devices with an etch stop layer on gate end-portions located above an isolation region | Ruilong Xie, Hoon Kim, Min Gyu Sung | 2017-04-18 |
| 9601387 | Method of making threshold voltage tuning using self-aligned contact cap | Xiuyu Cai, Hoon Kim | 2017-03-21 |
| 9589850 | Method for controlled recessing of materials in cavities in IC devices | Kisup Chung, Sivananda K. Kanakasabapathy | 2017-03-07 |
| 9583584 | Methods for producing integrated circuits using long and short regions and integrated circuits produced from such methods | Injo Ok | 2017-02-28 |
| 9552992 | Co-fabrication of non-planar semiconductor devices having different threshold voltages | Hoon Kim, Min Gyu Sung, Ruilong Xie | 2017-01-24 |
| 9543215 | Punch-through-stop after partial fin etch | Kwan-Yong Lim, Steven Bentley | 2017-01-10 |
| 9536793 | Self-aligned gate-first VFETs using a gate spacer recess | John H. Zhang, Kwan-Yong Lim, Steven Bentley | 2017-01-03 |
| 9508604 | Methods of forming punch through stop regions on FinFET devices on CMOS-based IC products using doped spacers | Min Gyu Sung, Hoon Kim, Ruilong Xie | 2016-11-29 |
| 9502308 | Methods for forming transistor devices with different source/drain contact liners and the resulting devices | Hoon Kim, Ruilong Xie, Min Gyu Sung | 2016-11-22 |
| 9502286 | Methods of forming self-aligned contact structures on semiconductor devices and the resulting devices | Ruilong Xie, Min Gyu Sung, Hoon Kim, Andre P. Labonte | 2016-11-22 |
| 9478538 | Methods for forming transistor devices with different threshold voltages and the resulting devices | Hoon Kim, Ruilong Xie, Min Gyu Sung | 2016-10-25 |
| 9478661 | Semiconductor device structures with self-aligned fin structure(s) and fabrication methods thereof | Ruilong Xie, Hoon Kim, Min Gyu Sung | 2016-10-25 |
| 9461171 | Methods of increasing silicide to epi contact areas and the resulting devices | Ruilong Xie, Hoon Kim, Naim Moumen, William J. Taylor, Jr. | 2016-10-04 |
| 9425103 | Methods of using a metal protection layer to form replacement gate structures for semiconductor devices | Ruilong Xie, Sean Xuan Lin | 2016-08-23 |
| 9425106 | Methods of performing fin cut etch processes for taper FinFET semiconductor devices and the resulting devices | Ruilong Xie, Min Gyu Sung, Hoon Kim | 2016-08-23 |