Issued Patents All Time
Showing 26–50 of 155 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11461237 | Methods and systems for translating virtual addresses in a virtual memory based system | Mohit Karve | 2022-10-04 |
| 11392386 | Program counter (PC)-relative load and store addressing for fused instructions | Nicholas R. Orzol, Christian Zoellin, Dung Q. Nguyen, Niels Fricke, Sheldon B. Levenstein +2 more | 2022-07-19 |
| 11327766 | Instruction dispatch routing | Eric M. Schwarz, Kurt A. Feiste, Michael J. Genden, Dung Q. Nguyen, Susan E. Eisen | 2022-05-10 |
| 11327757 | Processor providing intelligent management of values buffered in overlaid architected and non-architected register files | Steven J. Battle, Kurt A. Feiste, Susan E. Eisen, Dung Q. Nguyen, Christian Zoellin +4 more | 2022-05-10 |
| 11301254 | Instruction streaming using state migration | Steven J. Battle, Joshua W. Bowman, Hung Q. Le, Dung Q. Nguyen | 2022-04-12 |
| 11275561 | Mixed precision floating-point multiply-add operation | Silvia M. Mueller, Andreas Wagner | 2022-03-15 |
| 11249757 | Handling and fusing load instructions in a processor | Bryan Lloyd, Dung Q. Nguyen, Sheldon B. Levenstein, Brian D. Barrick, Christian Zoellin | 2022-02-15 |
| 11226817 | Prefetching workloads with dependent pointers | Mohit Karve, Donald R. Stence, John B. Griswell, Jr. | 2022-01-18 |
| 11188328 | Compute array of a processor with mixed-precision numerical linear algebra support | Jose E. Moreira, Brett Olsson, Silvia M. Mueller, Andreas Wagner | 2021-11-30 |
| 11188340 | Multiple streams execution for hard-to-predict branches in a microprocessor | Hung Q. Le, Dung Q. Nguyen | 2021-11-30 |
| 11182458 | Three-dimensional lane predication for matrix operations | Brett Olsson, Jose E. Moreira, Silvia M. Mueller, Andreas Wagner | 2021-11-23 |
| 11182164 | Pairing issue queues for complex instructions and instruction fusion | Brian D. Barrick, John B. Griswell, Jr., Dung Q. Nguyen | 2021-11-23 |
| 11163571 | Fusion to enhance early address generation of load instructions in a microprocessor | Brian D. Barrick, Sundeep Chadha, Sheldon B. Levenstein, Phillip G. Williams, Niels Fricke +2 more | 2021-11-02 |
| 11163577 | Selectively supporting static branch prediction settings only in association with processor-designated types of instructions | Sheldon B. Levenstein, David S. Levitan | 2021-11-02 |
| 11163695 | Methods and systems for translating virtual addresses in a virtual memory based system | Mohit Karve | 2021-11-02 |
| 11157276 | Thread-based organization of slice target register file entry in a microprocessor to permit writing scalar or vector data to portions of a single register file entry | Steven J. Battle, Maarten J. Boersma, Niels Fricke, Hung Q. Le, Dung Q. Nguyen | 2021-10-26 |
| 11150907 | Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries | Salma Ayub, Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le +1 more | 2021-10-19 |
| 11144323 | Independent mapping of threads | Sam Gat-Shang Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira +1 more | 2021-10-12 |
| 11138089 | Performance benchmark generation | Shricharan Srivatsan, Vivek Britto, Aishwarya Dhandapani, Tharunachalam Pindicura, John A. Schumann | 2021-10-05 |
| 11132198 | Instruction handling for accumulation of register results in a microprocessor | Maarten J. Boersma, Andreas Wagner, Jose E. Moreira, Hung Q. Le, Silvia M. Mueller +1 more | 2021-09-28 |
| 11119932 | Operation of a multi-slice processor implementing adaptive prefetch control | Bradly G. Frey, George W. Rohrbaugh, III | 2021-09-14 |
| 11119774 | Slice-target register file for microprocessor | Dung Q. Nguyen, Hung Q. Le, Sam Gat-Shang Chu | 2021-09-14 |
| 11119772 | Check pointing of accumulator register results in a microprocessor | Steven J. Battle, Brian D. Barrick, Susan E. Eisen, Andreas Wagner, Dung Q. Nguyen +2 more | 2021-09-14 |
| 11106466 | Decoupling of conditional branches | Nicholas R. Orzol, Michael J. Genden, Hung Q. Le, Dung Q. Nguyen, Eula Faye Abalos Tolentino | 2021-08-31 |
| 11093248 | Prefetch queue allocation protection bubble in a processor | Vivek Britto, Mohit Karve, George W. Rohrbaugh, III | 2021-08-17 |