Issued Patents All Time
Showing 51–75 of 155 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11093246 | Banked slice-target register file for wide dataflow execution in a microprocessor | Maarten J. Boersma, Niels Fricke, Michael K. Kroener, Hung Q. Le, Dung Q. Nguyen | 2021-08-17 |
| 11080060 | Preventing operand store compare conflicts using conflict address data tables | Ehsan Fatehi, John B. Griswell, Jr. | 2021-08-03 |
| 11061681 | Instruction streaming using copy select vector | Steven J. Battle, Joshua W. Bowman, Hung Q. Le, Dung Q. Nguyen | 2021-07-13 |
| 10996995 | Saving and restoring a transaction memory state | Steven J. Battle, Dung Q. Nguyen, Hung Q. Le, James Wilson Bishop, Susan E. Eisen | 2021-05-04 |
| 10983800 | Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices | Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti +1 more | 2021-04-20 |
| 10983797 | Program instruction scheduling | Christian Zoellin, Phillip G. Williams, Dung Q. Nguyen, Hung Q. Le, Jessica Hui-Chun Tseng +3 more | 2021-04-20 |
| 10963249 | Processor prefetcher mode governor for switching between prefetch modes | Mohit Karve, Vivek Britto, George W. Rohrbaugh, III | 2021-03-30 |
| 10949205 | Implementation of execution compression of instructions in slice target register file mapper | Joshua W. Bowman, Dung Q. Nguyen, Hung Q. Le, Maureen A. Delaney, Cliff Kucharski +1 more | 2021-03-16 |
| 10942745 | Fast multi-width instruction issue in parallel slice processor | Salma Ayub, Jeffrey C. Brownscheidle, Sundeep Chadha, Dung Q. Nguyen, Tu-An T. Nguyen +1 more | 2021-03-09 |
| 10936321 | Instruction chaining | Kurt A. Feiste, Joshua W. Bowman, Christopher M. Mueller, Dung Q. Nguyen, Deepak Singh | 2021-03-02 |
| 10909034 | Issue queue snooping for asynchronous flush and restore of distributed history buffer | David R. Terry, Dung Q. Nguyen, Joshua W. Bowman, Steven J. Battle, Sundeep Chadha +2 more | 2021-02-02 |
| 10884742 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra +2 more | 2021-01-05 |
| 10884753 | Issue queue with dynamic shifting between ports | Balaram Sinharoy, Joel A. Silberman | 2021-01-05 |
| 10838857 | Multi-section garbage collection | Giles R. Frazier, Michael K. Gschwind, Younes Manton, Karl M. Taylor | 2020-11-17 |
| 10831501 | Managing an issue queue for fused instructions and paired instructions in a microprocessor | Michael J. Genden, Hung Q. Le, Dung Q. Nguyen | 2020-11-10 |
| 10831498 | Managing an issue queue for fused instructions and paired instructions in a microprocessor | Michael J. Genden, Hung Q. Le, Dung Q. Nguyen | 2020-11-10 |
| 10831481 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra +2 more | 2020-11-10 |
| 10824430 | Resolving operand store compare conflicts | Ehsan Fatehi | 2020-11-03 |
| 10802964 | Multi-section garbage collection method | Giles R. Frazier, Michael K. Gschwind, Younes Manton, Karl M. Taylor | 2020-10-13 |
| 10776275 | Cache data replacement in a networked computing system using reference states based on reference attributes | Bernard C. Drerup, Mohit Karve | 2020-09-15 |
| 10747545 | Dual compare of least-significant-bit for dependency wake up from a fused instruction tag in a microprocessor | Michael J. Genden, Hung Q. Le, Dung Q. Nguyen | 2020-08-18 |
| 10740107 | Operation of a multi-slice processor implementing load-hit-store handling | Salma Ayub, Joshua W. Bowman, Jeffrey C. Brownscheidle, Kurt A. Feiste, Dung Q. Nguyen +1 more | 2020-08-11 |
| 10691459 | Converting multiple instructions into a single combined instruction with an extension opcode | Giles R. Frazier, Hung Q. Le, Jose E. Moreira | 2020-06-23 |
| 10684856 | Converting multiple instructions into a single combined instruction with an extension opcode | Giles R. Frazier, Hung Q. Le, Jose E. Moreira | 2020-06-16 |
| 10671394 | Prefetch stream allocation for multithreading systems | Vivek Britto, George W. Rohrbaugh, III, Mohit Karve | 2020-06-02 |