Issued Patents All Time
Showing 51–75 of 132 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6624476 | Semiconductor-on-insulator (SOI) substrate having selective dopant implant in insulator layer and method of fabricating | Simon S. Chan, Qi Xiang | 2003-09-23 |
| 6624037 | XE preamorphizing implantation | Che-Hoo Ng | 2003-09-23 |
| 6613643 | Structure, and a method of realizing, for efficient heat removal on SOI | Srinath Krishnan | 2003-09-02 |
| 6605513 | Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing | Eric N. Paton, Ercan Adem, Jacques Bertrand, Paul R. Besser, John Foster +4 more | 2003-08-12 |
| 6602781 | Metal silicide gate transistors | Qi Xiang, Paul R. Besser, John Foster, Paul L. King, Eric N. Paton | 2003-08-05 |
| 6589866 | Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process | Paul R. Besser, Qi Xiang | 2003-07-08 |
| 6583012 | Semiconductor devices utilizing differently composed metal-based in-laid gate electrodes | Qi Xiang, Paul R. Besser | 2003-06-24 |
| 6562718 | Process for forming fully silicided gates | Qi Xiang, Ercan Adem, Jacques Bertrand, Paul R. Besser, John Foster +5 more | 2003-05-13 |
| 6559051 | Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors | Paul R. Besser, Paul L. King, Eric N. Paton, Qi Xang | 2003-05-06 |
| 6552395 | Higher thermal conductivity glass for SOI heat removal | — | 2003-04-22 |
| 6544872 | Dopant implantation processing for improved source/drain interface with metal silicides | Qi Xiang, George Jonathan Kluth | 2003-04-08 |
| 6534379 | Linerless shallow trench isolation method | Philip A. Fisher, Ming-Ren Lin | 2003-03-18 |
| 6534822 | Silicon on insulator field effect transistor with a double Schottky gate structure | Qi Xiang | 2003-03-18 |
| 6528362 | Metal gate with CVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process | Paul R. Besser, Qi Xiang | 2003-03-04 |
| 6518185 | Integration scheme for non-feature-size dependent cu-alloy introduction | Pin-Chin Connie Wang, Fei Wang, Kashmir Sahota, Steven C. Avanzino, Amit P. Marathe +2 more | 2003-02-11 |
| 6518107 | Non-arsenic N-type dopant implantation for improved source/drain interfaces with nickel silicides | Qi Xiang, Paul R. Besser | 2003-02-11 |
| 6518113 | Doping of thin amorphous silicon work function control layers of MOS gate electrodes | — | 2003-02-11 |
| 6518154 | Method of forming semiconductor devices with differently composed metal-based gate electrodes | Qi Xiang, Paul R. Besser | 2003-02-11 |
| 6518167 | Method of forming a metal or metal nitride interface layer between silicon nitride and copper | Lu You, Paul R. Besser, Jeremias D. Romero, Pin-Chin Connie Wang, Minh Quoc Tran | 2003-02-11 |
| 6500743 | Method of copper-polysilicon T-gate formation | Sergey Lopatin, Steven C. Avanzino | 2002-12-31 |
| 6495887 | Argon implantation after silicidation for improved floating-body effects | Srinath Krishnan, Witold P. Maszara | 2002-12-17 |
| 6492258 | METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-&mgr;M AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY | Minh Van Ngo, Paul R. Besser, John Caffall, Nick Maccrae, Richard J. Huang +1 more | 2002-12-10 |
| 6492209 | Selectively thin silicon film for creating fully and partially depleted SOI on same wafer | Srinath Krishnan, Witold P. Maszara | 2002-12-10 |
| 6492249 | High-K gate dielectric process with process with self aligned damascene contact to damascene gate and a low-k inter level dielectric | Qi Xiang, Ming-Ren Lin | 2002-12-10 |
| 6486062 | Selective deposition of amorphous silicon for formation of nickel silicide with smooth interface on N-doped substrate | George Jonathan Kluth | 2002-11-26 |