Issued Patents All Time
Showing 26–50 of 132 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6861325 | Methods for fabricating CMOS-compatible lateral bipolar junction transistors | James Pan | 2005-03-01 |
| 6852586 | Self assembly of conducting polymer for formation of polymer memory cell | Suzette K. Pangrle, Uzodinma Okoroanyanwu, Nicholas H. Tripsas | 2005-02-08 |
| 6835655 | Method of implanting copper barrier material to improve electrical performance | Paul R. Besser, Sergey Lopatin | 2004-12-28 |
| 6815340 | Method of forming an electroless nucleation layer on a via bottom | Sergey Lopatin, Paul R. Besser, Pin-Chin Connie Wang | 2004-11-09 |
| 6803267 | Silicon containing material for patterning polymeric memory element | Ramkumar Subramanian, Christopher F. Lyons, Patrick K. Cheung, Angela T. Hui, Ashok M. Khathuria +5 more | 2004-10-12 |
| 6787458 | Polymer memory device formed in via opening | Nicholas H. Tripsas, Suzette K. Pangrle, Uzodinma Okoroanyanwu, Angela T. Hui, Christopher F. Lyons +7 more | 2004-09-07 |
| 6787436 | Silicide-silicon contacts for reduction of MOSFET source-drain resistances | Witold P. Maszara | 2004-09-07 |
| 6784506 | Silicide process using high K-dielectrics | Qi Xiang, Paul R. Besser, John Foster, Paul L. King, Eric N. Paton | 2004-08-31 |
| 6770905 | Implantation for the formation of CuX layer in an organic memory device | Suzette K. Pangrle, Sergey Lopatin, Minh Van Ngo | 2004-08-03 |
| 6765303 | FinFET-based SRAM cell | Zoran Krivokapic, Judy Xilin An | 2004-07-20 |
| 6764912 | Passivation of nitride spacer | John Foster, Eric N. Paton, Qi Xiang, Paul R. Besser, Paul L. King | 2004-07-20 |
| 6759308 | Silicon on insulator field effect transistor with heterojunction gate | Qi Xiang | 2004-07-06 |
| 6753247 | Method(s) facilitating formation of memory cell(s) and patterned conductive | Uzodinma Okoroanyanwu, Suzette K. Pangrle, Nicholas H. Tripsas, Mark S. Chang, Ramkumar Subramanian +1 more | 2004-06-22 |
| 6727546 | Self-aligned triple gate silicon-on-insulator (SOI) device | Zoran Krivokapic | 2004-04-27 |
| 6724087 | Laminated conductive lines and methods of forming the same | Paul R. Besser, Sergey Lopatin, Lu You | 2004-04-20 |
| 6716684 | Method of making a self-aligned triple gate silicon-on-insulator device | Zoran Krivokapic | 2004-04-06 |
| 6716686 | Method for forming channels in a finfet device | Judy Xilin An, Bin Yu | 2004-04-06 |
| 6710452 | Coherent diffusion barriers for integrated circuit interconnects | Pin-Chin Connie Wang, Suzette K. Pangrle, Amit P. Marathe | 2004-03-23 |
| 6709982 | Double spacer FinFET formation | Judy Xilin An, Haihong Wang, Bin Yu | 2004-03-23 |
| 6703308 | Method of inserting alloy elements to reduce copper diffusion and bulk diffusion | Paul R. Besser, Sergey Lopatin, Alline F. Myers, Phin-Chin Connie Wang | 2004-03-09 |
| 6703307 | Method of implantation after copper seed deposition | Sergey Lopatin, Paul R. Besser | 2004-03-09 |
| 6667552 | Low dielectric metal silicide lined interconnection system | — | 2003-12-23 |
| 6660608 | Method for manufacturing CMOS device having low gate resistivity using aluminum implant | — | 2003-12-09 |
| 6645797 | Method for forming fins in a FinFET device using sacrificial carbon layer | Srikanteswara Dakshina-Murthy, Cyrus E. Tabery, Haihong Wang, Chih-Yuh Yang, Bin Yu | 2003-11-11 |
| 6642590 | Metal gate with PVD amorphous silicon layer and barrier layer for CMOS devices and method of making with a replacement gate process | Paul R. Besser, Qi Xiang | 2003-11-04 |