Issued Patents All Time
Showing 76–100 of 132 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6475874 | Damascene NiSi metal gate high-k transistor | Qi Xiang, Paul R. Besser, John Foster, Paul L. King, Eric N. Paton | 2002-11-05 |
| 6465334 | Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors | Paul R. Besser, Paul L. King, Eric N. Paton, Qi Xiang | 2002-10-15 |
| 6465309 | Silicide gate transistors | Qi Xiang, Paul R. Besser, John Foster, Paul L. King, Eric N. Paton | 2002-10-15 |
| 6458679 | Method of making silicide stop layer in a damascene semiconductor structure | Eric N. Paton, Paul R. Besser, Qi Xiang, Paul L. King, John Foster | 2002-10-01 |
| 6452250 | Stacked integrated circuit and capacitor structure containing via structures | — | 2002-09-17 |
| 6440867 | Metal gate with PVD amorphous silicon and silicide for CMOS devices and method of making the same with a replacement gate process | Paul R. Besser, Qi Xiang | 2002-08-27 |
| 6440868 | Metal gate with CVD amorphous silicon layer and silicide for CMOS devices and method of making with a replacement gate process | Paul R. Besser, Qi Xiang | 2002-08-27 |
| 6436840 | Metal gate with CVD amorphous silicon layer and a barrier layer for CMOS devices and method of making with a replacement gate process | Paul R. Besser, Qi Xiang | 2002-08-20 |
| 6433379 | Tantalum anodization for in-laid copper metallization capacitor | Sergey Lopatin, Steven C. Avanzino, Qi Xiang | 2002-08-13 |
| 6417030 | Leaky lower interface for reduction of floating body effect in SOI devices | Donald L. Wollesen | 2002-07-09 |
| 6403492 | Method of manufacturing semiconductor devices with trench isolation | Darin A. Chan | 2002-06-11 |
| 6396108 | Self-aligned double gate silicon-on-insulator (SOI) device | Zoran Krivokapic | 2002-05-28 |
| 6392280 | Metal gate with PVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process | Paul R. Besser, Qi Xiang | 2002-05-21 |
| 6380057 | Enhancement of nickel silicide formation by use of nickel pre-amorphizing implant | George Jonathan Kluth, Paul R. Besser, Paul L. King | 2002-04-30 |
| 6376336 | Frontside SOI gettering with phosphorus doping | — | 2002-04-23 |
| 6376343 | Reduction of metal silicide/silicon interface roughness by dopant implantation processing | Paul R. Besser, Qi Xiang | 2002-04-23 |
| 6368950 | Silicide gate transistors | Qi Xiang, Paul R. Besser, John Foster, Paul L. King, Eric N. Paton | 2002-04-09 |
| 6342414 | Damascene NiSi metal gate high-k transistor | Qi Xiang, Paul R. Besser, John Foster, Paul L. King, Eric N. Paton | 2002-01-29 |
| 6329718 | Method for reducing stress-induced voids for 0.25m.mu. and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby | Minh Van Ngo, Paul R. Besser, John Caffall, Nick Maccrae, Richard J. Huang +1 more | 2001-12-11 |
| 6326247 | Method of creating selectively thin silicon/oxide for making fully and partially depleted SOI on same waffer | Srinath Krishnan | 2001-12-04 |
| 6300203 | Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors | Paul R. Besser, Qi Xang, Paul L. King, Eric N. Paton | 2001-10-09 |
| 6297157 | Time ramped method for plating of high aspect ratio semiconductor vias and channels | Sergey Lopatin | 2001-10-02 |
| 6291278 | Method of forming transistors with self aligned damascene gate contact | Qi Xiang, Ming-Ren Lin | 2001-09-18 |
| 6279147 | Use of an existing product map as a background for making test masks | Ramkumar Subramanian, Todd P. Lukanc | 2001-08-21 |
| 6271132 | Self-aligned source and drain extensions fabricated in a damascene contact and gate process | Qi Xiang, Ming-Ren Lin | 2001-08-07 |