Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6806147 | Method and apparatus for suppressing the channeling effect in high energy deep well implantation | Bin Yu | 2004-10-19 |
| 6756600 | Ion implantation with improved ion source life expectancy | Emi Ishida, Jaime M. Reyes, Jinning Liu, Sandeep Mehta | 2004-06-29 |
| 6642152 | Method for ultra thin resist linewidth reduction using implantation | Scott A. Bell, Anne E. Sanderfer, Christopher Lee Pike | 2003-11-04 |
| 6624037 | XE preamorphizing implantation | Matthew S. Buynoski | 2003-09-23 |
| 6514833 | Method of inhibiting lateral diffusion between adjacent wells by introducing carbon or fluorine ions into bottom of STI groove | Emi Ishida | 2003-02-04 |
| 6503801 | Non-uniform channel profile via enhanced diffusion | Richard P. Rouse, Judy Xilin An | 2003-01-07 |
| 6459141 | Method and apparatus for suppressing the channeling effect in high energy deep well implantation | Bin Yu | 2002-10-01 |
| 6452198 | Minimized contamination of semiconductor wafers within an implantation system | Balaraman Mani, Bill Chen | 2002-09-17 |
| 6445030 | Flash memory erase speed by fluorine implant or fluorination | Yider Wu, Jean Y. Yang, Hidehiko Shiraiwa | 2002-09-03 |
| 6380041 | Semiconductor with laterally non-uniform channel doping profile and manufacturing method therefor | Geoffrey Choh-Fei Yeap, Ognjen Milic | 2002-04-30 |
| 6288405 | Method for determining ultra shallow junction dosimetry | — | 2001-09-11 |
| 6235636 | Resist removal by polishing | Matthew S. Buynoski | 2001-05-22 |
| 6232048 | Method for preparing narrow photoresist lines | Matthew S. Buynoski, Bhanwar Singh, Shekhan Pramanick, Subhash Gupta | 2001-05-15 |
| 6229177 | Semiconductor with laterally non-uniform channel doping profile | Geoffrey Choh-Fei Yeap, Ognjen Milic | 2001-05-08 |
| 6191012 | Method for forming a shallow junction in a semiconductor device using antimony dimer | Matthew S. Buynoski | 2001-02-20 |
| 6146944 | Large angle implantation to prevent field turn-on under select gate transistor field oxide region for non-volatile memory devices | Yue-Song He, Pau-Ling Chen | 2000-11-14 |
| 6136674 | Mosfet with gate plug using differential oxide growth | Judy Xilin An | 2000-10-24 |
| 6087255 | Conductive layer with anti-reflective surface portion | Shekhar Pramanick, Bhanwar Singh | 2000-07-11 |
| 6074937 | End-of-range damage suppression for ultra-shallow junction formation | Shekhar Pramanick, Emi Ishida | 2000-06-13 |
| 6008098 | Ultra shallow junction formation using amorphous silicon layer | Shekhar Pramanick | 1999-12-28 |
| 5940735 | Reduction of charge loss in nonvolatile memory cells by phosphorus implantation into PECVD nitride/oxynitride films | Sunil Mehta | 1999-08-17 |
| 5876903 | Virtual hard mask for etching | Bhanwar Singh, Shekhar Pramanick, Subash Gupta | 1999-03-02 |
| 5841179 | Conductive layer with anti-reflective surface portion | Shekhar Pramanick, Bhanwar Singh | 1998-11-24 |