Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6846716 | Integrated circuit device and method therefor | Srinivas Jallepalli, Yongjoo Jeon, James D. Burnett, Rana P. Singh, Paul A. Grudowski | 2005-01-25 |
| 6753242 | Integrated circuit device and method therefor | Srinivas Jallepalli, Yongjoo Jeon | 2004-06-22 |
| 6380041 | Semiconductor with laterally non-uniform channel doping profile and manufacturing method therefor | Ognjen Milic, Che-Hoo Ng | 2002-04-30 |
| 6229177 | Semiconductor with laterally non-uniform channel doping profile | Ognjen Milic, Che-Hoo Ng | 2001-05-08 |
| 6144063 | Ultra-thin oxide for semiconductors | Zoran Krivokapic, Ming-Ren Lin | 2000-11-07 |
| 6100558 | Semiconductor device having enhanced gate capacitance by using both high and low dielectric materials | Zoran Krivokapic, Srinath Krishnan, Matthew S. Buynoski | 2000-08-08 |
| 6096586 | MOS device with self-compensating V.sub.aT -implants | Ognjen Milic-Strkalj | 2000-08-01 |
| 6093594 | CMOS optimization method utilizing sacrificial sidewall spacer | Qi Xiang, Ming-Ren Lin | 2000-07-25 |
| 6087209 | Formation of low resistance, ultra shallow LDD junctions employing a sub-surface, non-amorphous implant | Akif Sultan, Shekhar Pramanick | 2000-07-11 |
| 6087208 | Method for increasing gate capacitance by using both high and low dielectric gate material | Zoran Krivokapic, Srinath Krishnan, Matthew S. Buynoski | 2000-07-11 |
| 6063682 | Ultra-shallow p-type junction having reduced sheet resistance and method for producing shallow junctions | Akif Sultan | 2000-05-16 |
| 5960322 | Suppression of boron segregation for shallow source and drain junctions in semiconductors | Qi Xiang, Srinath Krishnan, Ming-Ren Lin | 1999-09-28 |