Issued Patents 2024
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12142524 | Via for component electrode connection | Chen-Hua Yu, Wen-Chih Chiou, Tsang-Jiuh Wu, Der-Chyang Yeh, Ming-Shih Yeh +1 more | 2024-11-12 |
| 12087745 | Package structure and manufacturing method thereof | Wei-Yu Chen, An-Jhih Su, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai +2 more | 2024-09-10 |
| 12080638 | Semiconductor device and method for manufacturing the same | Kuo-Chiang Ting, Shang-Yun Hou, Tu-Hao Yu, Chia-Hao Hsu, Pin-Tso Lin +1 more | 2024-09-03 |
| 12051652 | Package structure and method of fabricating the same | Shih-Ting Lin, Chen-Hua Yu, Szu-Wei Lu | 2024-07-30 |
| 12033898 | Method of fabricating a FinFET device | Joanna Chaw Yane Yin, Kuo-Chiang Ting, Kuang-Hsin Chen | 2024-07-09 |
| 12020953 | Fan-out structure and method of fabricating the same | Chen-Hua Yu, An-Jhih Su, Der-Chyang Yeh, Hsien-Wei Chen, Wei-Yu Chen | 2024-06-25 |
| 12015023 | Integrated circuit package and method of forming same | Shang-Yun Hou, Sung-Hui Huang, Kuan-Yu Huang, Hsien-Pin Hu, Yushun Lin +8 more | 2024-06-18 |
| 12009335 | Structure and method of forming a joint assembly | Ying-Ju Chen, An-Jhih Su, Hsien-Wei Chen, Der-Chyang Yeh, Chen-Hua Yu | 2024-06-11 |
| 11978714 | Encapsulated package including device dies connected via interconnect die | Kuo-Chiang Ting, Shang-Yun Hou, Tu-Hao Yu, Chia-Hao Hsu, Ting-Yu Yeh | 2024-05-07 |
| 11967546 | Giga interposer integration through Chip-On-Wafer-On-Substrate | Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang +5 more | 2024-04-23 |
| 11961779 | 3DIC packaging with hot spot thermal management features | Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Shin-Puu Jeng | 2024-04-16 |
| 11961800 | Via for semiconductor device connection and methods of forming the same | Chen-Hua Yu, An-Jhih Su, Wen-Chih Chiou, Tsang-Jiuh Wu, Der-Chyang Yeh +1 more | 2024-04-16 |