Issued Patents 2019
Showing 201–225 of 354 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10297667 | Fin field-effect transistor for input/output device integrated with nanosheet field-effect transistor | Chun Wing Yeung, Chen Zhang, Peng Xu, Huiming Bu | 2019-05-21 |
| 10297507 | Self-aligned vertical field-effect transistor with epitaxially grown bottom and top source drain regions | Shogo Mochizuki, Tenko Yamashita, Chen Zhang | 2019-05-21 |
| 10297448 | SiGe fins formed on a substrate | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-05-21 |
| 10290633 | CMOS compatible fuse or resistor using self-aligned contacts | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-05-14 |
| 10290574 | Embedded metal-insulator-metal (MIM) decoupling capacitor in monolitic three-dimensional (3D) integrated circuit (IC) structure | Geng Wang, Chengwen Pei, Juntao Li | 2019-05-14 |
| 10283504 | Vertical FET with reduced parasitic capacitance | Xin Miao, Philip J. Oldiges, Wenyu Xu, Chen Zhang | 2019-05-07 |
| 10283625 | Integrated strained stacked nanosheet FET | Ramachandra Divakaruni, Juntao Li, Xin Miao | 2019-05-07 |
| 10283606 | Vertical fin with a gate structure having a modified gate geometry | Peng Xu | 2019-05-07 |
| 10283602 | Fully depleted SOI device for reducing parasitic back gate capacitance | Ramachandra Divakaruni | 2019-05-07 |
| 10283601 | Strained silicon germanium fin with block source/drain epitaxy and improved overlay capacitance | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2019-05-07 |
| 10283592 | Approach to minimization of strain loss in strained fin field effect transistors | Zhenxing Bi, Juntao Li, Peng Xu | 2019-05-07 |
| 10283586 | Capacitors | Veeraraghavan S. Basker, Christopher J. Penny, Theodorus E. Standaert, Junli Wang | 2019-05-07 |
| 10283565 | Resistive memory with a plurality of resistive random access memory cells each comprising a transistor and a resistive element | Peng Xu, Juntao Li, Choonghyun Lee | 2019-05-07 |
| 10283406 | Fabrication of self-aligned gate contacts and source/drain contacts directly above gate electrodes and source/drains | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-05-07 |
| 10276569 | Minimizing shorting between FinFET epitaxial regions | Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty | 2019-04-30 |
| 10276659 | Air gap adjacent a bottom source/drain region of vertical transistor device | Ruilong Xie, Chun-Chen Yeh, Tenko Yamashita | 2019-04-30 |
| 10276658 | FinFET devices | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-04-30 |
| 10276442 | Wrap-around contacts formed with multiple silicide layers | Ruilong Xie, Julien Frougier, Adra Carr, Nicolas Loubet | 2019-04-30 |
| 10269644 | Fin pitch scaling for high voltage devices and low voltage devices on the same wafer | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-04-23 |
| 10269983 | Stacked nanosheet field-effect transistor with air gap spacers | Julien Frougier, Ruilong Xie, Hui Zang, Tenko Yamashita, Chun-Chen Yeh | 2019-04-23 |
| 10269931 | Vertical transport field effect transistor with precise gate length definition | Marc A. Bergendahl, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan | 2019-04-23 |
| 10269920 | Nanosheet transistors having thin and thick gate dielectric material | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2019-04-23 |
| 10269790 | Forming horizontal bipolar junction transistor compatible with nanosheets | Juntao Li, Geng Wang, Qintao Zhang | 2019-04-23 |
| 10262861 | Forming a fin cut in a hardmask | Zhenxing Bi, Juntao Li, Peng Xu | 2019-04-16 |
| 10263100 | Buffer regions for blocking unwanted diffusion in nanosheet transistors | Zhenxing Bi, Juntao Li, Peng Xu | 2019-04-16 |