Issued Patents 2019
Showing 151–175 of 354 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10347752 | Semiconductor structures having increased channel strain using fin release in gate regions | Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim | 2019-07-09 |
| 10347719 | Nanosheet transistors on bulk material | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2019-07-09 |
| 10347727 | Fin-type FET with low source or drain contact resistance | Juntao Li, Heng Wu, Peng Xu | 2019-07-09 |
| 10340368 | Fin formation in fin field effect transistors | Bruce B. Doris, Hong He, Ali Khakifirooz, Yunpeng Yin | 2019-07-02 |
| 10340341 | Self-limiting and confining epitaxial nucleation | Robin Hsin Kuo Chao, Nicolas Loubet | 2019-07-02 |
| 10340364 | H-shaped VFET with increased current drivability | Chen Zhang, Tenko Yamashita, Xin Miao, Wenyu Xu | 2019-07-02 |
| 10340292 | Extremely thin silicon-on-insulator silicon germanium device without edge strain relaxation | Juntao Li, Zuoguang Liu, Xin Miao | 2019-07-02 |
| 10332986 | Formation of inner spacer on nanosheet MOSFET | Zhenxing Bi, Juntao Li, Peng Xu | 2019-06-25 |
| 10332999 | Method and structure of forming fin field-effect transistor without strain relaxation | Juntao Li, Choonghyun Lee, Peng Xu, Heng Wu | 2019-06-25 |
| 10332983 | Vertical field-effect transistors including uniform gate lengths | Choonghyun Lee, Juntao Li, Heng Wu, Peng Xu | 2019-06-25 |
| 10332961 | Inner spacer for nanosheet transistors | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2019-06-25 |
| 10332962 | Nanosheet semiconductor structure with inner spacer formed by oxidation | Xin Miao, Chen Zhang, Wenyu Xu | 2019-06-25 |
| 10333000 | Forming strained channel with germanium condensation | Shogo Mochizuki, Jie Yang | 2019-06-25 |
| 10332880 | Vertical fin resistor devices | Zhenxing Bi, Peng Xu | 2019-06-25 |
| 10332796 | Fin pitch scaling for high voltage devices and low voltage devices on the same wafer | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-06-25 |
| 10332799 | Vertical silicon/silicon-germanium transistors with multiple threshold voltages | Zhenxing Bi, Juntao Li, Peng Xu | 2019-06-25 |
| 10332800 | Vertical field effect transistor having U-shaped top spacer | Xin Miao, Wenyu Xu, Chen Zhang | 2019-06-25 |
| 10332802 | Hybrid-channel nano-sheets FETs | Zhenxing Bi, Peng Xu, Wenyu Xu | 2019-06-25 |
| 10326022 | Self-aligned gate cut with polysilicon liner oxidation | Peng Xu | 2019-06-18 |
| 10326019 | Fully-depleted CMOS transistors with U-shaped channel | Robert H. Dennard, Bruce B. Doris, Terence B. Hook | 2019-06-18 |
| 10326020 | Structure and method for forming strained FinFET by cladding stressors | Juntao Li | 2019-06-18 |
| 10326017 | Formation of a bottom source-drain for vertical field-effect transistors | Marc A. Bergendahl, Fee Li Lie, Shogo Mochizuki, Junli Wang | 2019-06-18 |
| 10325817 | Semiconductor fin patterning techniques to achieve uniform fin profiles for fin field effect transistors | Zhenxing Bi, Juntao Li, Peng Xu | 2019-06-18 |
| 10325995 | Field effect transistor air-gap spacers with an etch-stop layer | Xin Miao, Wenyu Xu, Chen Zhang | 2019-06-18 |
| 10325999 | Contact area to trench silicide resistance reduction by high-resistance interface removal | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-06-18 |