JW

Junli Wang

IBM: 72 patents #18 of 11,143Top 1%
Globalfoundries: 4 patents #101 of 837Top 15%
SS Stmicroelectronics Sa: 4 patents #10 of 130Top 8%
Overall (2019): #129 of 560,194Top 1%
73
Patents 2019

Issued Patents 2019

Showing 25 most recent of 73 patents

Patent #TitleCo-InventorsDate
10516064 Multiple width nanosheet devices Kangguo Cheng, Lawrence A. Clevenger, Carl Radens, John H. Zhang 2019-12-24
10515859 Extra gate device for nanosheet Bruce B. Doris, Terence B. Hook 2019-12-24
10504889 Integrating a junction field effect transistor into a vertical field effect transistor Brent A. Anderson, Huiming Bu, Terence B. Hook, Xuefeng Liu 2019-12-10
10497629 Self-aligned punch through stopper liner for bulk FinFET Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2019-12-03
10475904 Methods of forming merged source/drain regions on integrated circuit products Hiroaki Niimi, Steven Bentley, Romain Lallement, Brent A. Anderson, Muthumanickam Sankarapandian 2019-11-12
10468491 Low resistance contact for transistors Lawrence A. Clevenger, Kirk D. Peterson, Baozhen Li, Terry A. Spooner, John E. Sheets, II 2019-11-05
10460990 Semiconductor via structure with lower electrical resistance Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Terry A. Spooner 2019-10-29
10453934 Vertical transport FET devices having air gap top spacer Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2019-10-22
10446670 Integration of strained silicon germanium PFET device and silicon NFET device for FINFET structures Bruce B. Doris, Hong He, Nicolas Loubet 2019-10-15
10438850 Semiconductor device with local connection Kangguo Cheng, Lawrence A. Clevenger, Carl Radens, John H. Zhang 2019-10-08
10431495 Semiconductor device with local connection Kangguo Cheng, Lawrence A. Clevenger, Carl Radens, John H. Zhang 2019-10-01
10418462 Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process Brent A. Anderson, Huiming Bu, Terence B. Hook, Fee Li Lie 2019-09-17
10418280 Fabrication of self-aligned gate contacts and source/drain contacts directly above gate electrodes and source/drains Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2019-09-17
10411128 Strained fin channel devices Kangguo Cheng, Lawrence A. Clevenger, Carl Radens, John H. Zhang 2019-09-10
10403740 Gate planarity for FinFET using dummy polish stop Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2019-09-03
10396069 Approach to fabrication of an on-chip resistor with a field effect transistor Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2019-08-27
10396185 Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures Bruce B. Doris, Hong He, Nicolas Loubet 2019-08-27
10388718 Metal-insulator-metal capacitor structure Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2019-08-20
10388576 Semiconductor device including dual trench epitaxial dual-liner contacts Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2019-08-20
10373905 Integrating metal-insulator-metal capacitors with air gap process flow Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2019-08-06
10374035 Bulk nanosheet with dielectric isolation Kangguo Cheng, Bruce B. Doris 2019-08-06
10361265 Precision BEOL resistors Baozhen Li, Kirk D. Peterson, John E. Sheets, II, Lawrence A. Clevenger, Chih-Chao Yang 2019-07-23
10347759 Vertical FET structure Brent A. Anderson, Huiming Bu, Fee Li Lie, Edward J. Nowak 2019-07-09
10340330 Precision BEOL resistors Baozhen Li, Kirk D. Peterson, John E. Sheets, II, Lawrence A. Clevenger, Chih-Chao Yang 2019-07-02
10340189 Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices Balasubramanian Pranatharthiharan, Ruilong Xie 2019-07-02