Issued Patents 2019
Showing 26–50 of 73 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10332955 | Precision BEOL resistors | Baozhen Li, Kirk D. Peterson, John E. Sheets, II, Lawrence A. Clevenger, Chih-Chao Yang | 2019-06-25 |
| 10332956 | Precision beol resistors | Baozhen Li, Kirk D. Peterson, John E. Sheets, II, Lawrence A. Clevenger, Chih-Chao Yang | 2019-06-25 |
| 10332796 | Fin pitch scaling for high voltage devices and low voltage devices on the same wafer | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2019-06-25 |
| 10326017 | Formation of a bottom source-drain for vertical field-effect transistors | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Shogo Mochizuki | 2019-06-18 |
| 10325999 | Contact area to trench silicide resistance reduction by high-resistance interface removal | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2019-06-18 |
| 10319816 | Silicon germanium fin channel formation | Hong He, Nicolas Loubet | 2019-06-11 |
| 10319852 | Forming eDRAM unit cell with VFET and via capacitance | Brent A. Anderson, Huiming Bu, Xuefeng Liu | 2019-06-11 |
| 10319640 | FinFET devices | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2019-06-11 |
| 10312323 | Bulk nanosheet with dielectric isolation | Kangguo Cheng, Bruce B. Doris | 2019-06-04 |
| 10312318 | Metal-insulator-metal capacitor structure | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2019-06-04 |
| 10312346 | Vertical transistor with variable gate length | Brent A. Anderson, Bassem M. Hamieh, Stuart A. Sieg | 2019-06-04 |
| 10312349 | Reducing resistance of bottom source/drain in vertical channel devices | Shogo Mochizuki | 2019-06-04 |
| 10312371 | Self-aligned shallow trench isolation and doping for vertical fin transistors | Brent A. Anderson, Fee Li Lie | 2019-06-04 |
| 10304941 | Replacement metal gate structures | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2019-05-28 |
| 10304741 | Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices | Balasubramanian Pranatharthiharan, Ruilong Xie | 2019-05-28 |
| 10297689 | Precise control of vertical transistor gate length | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2019-05-21 |
| 10297448 | SiGe fins formed on a substrate | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2019-05-21 |
| 10290633 | CMOS compatible fuse or resistor using self-aligned contacts | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2019-05-14 |
| 10283418 | Method of forming silicon germanium and silicon fins on oxide from bulk wafer | Hong He, James Kuss, Nicolas Loubet | 2019-05-07 |
| 10283636 | Vertical FET with strained channel | Shogo Mochizuki | 2019-05-07 |
| 10283586 | Capacitors | Veeraraghavan S. Basker, Kangguo Cheng, Christopher J. Penny, Theodorus E. Standaert | 2019-05-07 |
| 10283406 | Fabrication of self-aligned gate contacts and source/drain contacts directly above gate electrodes and source/drains | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2019-05-07 |
| 10276558 | Electrostatic discharge protection using vertical fin CMOS technology | Brent A. Anderson, Huiming Bu, Terence B. Hook, Xuefeng Liu, Miaomiao Wang | 2019-04-30 |
| 10276658 | FinFET devices | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2019-04-30 |
| 10269644 | Fin pitch scaling for high voltage devices and low voltage devices on the same wafer | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2019-04-23 |