Issued Patents 2019
Showing 1–25 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10515965 | Method to induce strain in finFET channels from an adjacent region | Pierre Morin | 2019-12-24 |
| 10505043 | Semiconductor device with fin and related methods | Pierre Morin | 2019-12-10 |
| 10497808 | Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer | Qing Liu | 2019-12-03 |
| 10490667 | Three-dimensional field effect device | Huimei Zhou, Su Chen Fan, Shogo Mochizuki, Peng Xu | 2019-11-26 |
| 10483393 | Method to induce strain in 3-D microfabricated structures | Pierre Morin | 2019-11-19 |
| 10453736 | Dielectric isolation in gate-all-around devices | Robin Hsin Kuo Chao, Kangguo Cheng, Pietro Montanini, Ruilong Xie | 2019-10-22 |
| 10446670 | Integration of strained silicon germanium PFET device and silicon NFET device for FINFET structures | Bruce B. Doris, Hong He, Junli Wang | 2019-10-15 |
| 10431683 | Method for making a semiconductor device with a compressive stressed channel | Shay Reboh, Emmanuel Augendre, Remi Coquand | 2019-10-01 |
| 10424651 | Forming nanosheet transistor using sacrificial spacer and inner spacers | Kangguo Cheng, Julien Frougier | 2019-09-24 |
| 10396185 | Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures | Bruce B. Doris, Hong He, Junli Wang | 2019-08-27 |
| 10388732 | Nanosheet field-effect transistors including a two-dimensional semiconducting material | Julien Frougier, Ruilong Xie, Kangguo Cheng, Juntao Li | 2019-08-20 |
| 10388760 | Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism | Julien Frougier, Ruilong Xie, Steven R. Bentley, Kangguo Cheng, Pietro Montanini | 2019-08-20 |
| 10367077 | Wrap around contact using sacrificial mandrel | Adra Carr, Kangguo Cheng | 2019-07-30 |
| 10366931 | Nanosheet devices with CMOS epitaxy and method of forming | Ruilong Xie, Cheng Chi, Pietro Montanini, Tenko Yamashita | 2019-07-30 |
| 10367062 | Co-integration of silicon and silicon-germanium channels for nanosheet devices | Michael A. Guillorn, Isaac Lauer | 2019-07-30 |
| 10367061 | Replacement metal gate and inner spacer formation in three dimensional structures using sacrificial silicon germanium | — | 2019-07-30 |
| 10354927 | Co-integration of tensile silicon and compressive silicon germanium | Pierre Morin, Yann Mignot | 2019-07-16 |
| 10340195 | Method to co-integrate SiGe and Si channels for finFET devices | Prasanna Khare, Qing Liu | 2019-07-02 |
| 10340341 | Self-limiting and confining epitaxial nucleation | Robin Hsin Kuo Chao, Kangguo Cheng | 2019-07-02 |
| 10340340 | Multiple-threshold nanosheet transistors | Ruqiang Bao, Michael A. Guillorn, Terence B. Hook, Robert R. Robison, Reinaldo Vega +1 more | 2019-07-02 |
| 10319816 | Silicon germanium fin channel formation | Hong He, Junli Wang | 2019-06-11 |
| 10319676 | Vertically integrated nanosheet fuse | Robin Hsin Kuo Chao, James J. Demarest | 2019-06-11 |
| 10304936 | Protection of high-K dielectric during reliability anneal on nanosheet structures | Sanjay C. Mehta, Vijay Narayanan, Muthumanickam Sankarapandian | 2019-05-28 |
| 10297665 | Co-integration of elastic and plastic relaxation on the same wafer | Stephen W. Bedell, Devendra K. Sadana | 2019-05-21 |
| 10283418 | Method of forming silicon germanium and silicon fins on oxide from bulk wafer | Hong He, James Kuss, Junli Wang | 2019-05-07 |