Issued Patents 2019
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10475904 | Methods of forming merged source/drain regions on integrated circuit products | Hiroaki Niimi, Steven Bentley, Romain Lallement, Brent A. Anderson, Junli Wang | 2019-11-12 |
| 10395936 | Wafer element with an adjusted print resolution assist feature | Yann Mignot | 2019-08-27 |
| 10396208 | Vertical transistors with improved top source/drain junctions | Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2019-08-27 |
| 10395938 | Wafer element with an adjusted print resolution assist feature | Yann Mignot | 2019-08-27 |
| 10374034 | Undercut control in isotropic wet etch processes | Chi-Chun Liu, Kristin Schmidt, Ekmini Anuja De Silva, Noel Arellano, Robin Hsin Kuo Chao +2 more | 2019-08-06 |
| 10304936 | Protection of high-K dielectric during reliability anneal on nanosheet structures | Nicolas Loubet, Sanjay C. Mehta, Vijay Narayanan | 2019-05-28 |
| 10256320 | Vertical field-effect-transistors having a silicon oxide layer with controlled thickness | Chi-Chun Liu, Sanjay C. Mehta, Luciana Meli, Kristin Schmidt, Ankit Vora | 2019-04-09 |
| 10256161 | Dual work function CMOS devices | Hemanth Jagannathan, Koji Watanabe | 2019-04-09 |
| 10242920 | Integrating and isolating NFET and PFET nanosheet transistors on a substrate | Michael A. Guillorn, Nicolas Loubet | 2019-03-26 |
| 10170326 | Wafer element with an adjusted print resolution assist feature | Yann Mignot | 2019-01-01 |