Issued Patents 2019
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10510620 | Work function metal patterning for N-P space between active nanostructures | Daniel Chanemougame, Steven R. Soss, Julien Frougier, Ruilong Xie | 2019-12-17 |
| 10497798 | Vertical field effect transistor with self-aligned contacts | Ruilong Xie, Puneet Harischandra Suvarna, Chanro Park, Min Gyu Sung, Lars Liebmann +2 more | 2019-12-03 |
| 10475904 | Methods of forming merged source/drain regions on integrated circuit products | Hiroaki Niimi, Romain Lallement, Brent A. Anderson, Junli Wang, Muthumanickam Sankarapandian | 2019-11-12 |
| 10461196 | Control of length in gate region during processing of VFET structures | Chanro Park, Ruilong Xie, Min Gyu Sung | 2019-10-29 |
| 10446451 | Method for forming replacement gate structures for vertical transistors | Steven R. Soss | 2019-10-15 |
| 10446659 | Negative capacitance integration through a gate contact | Rohit Galatage, Puneet Harischandra Suvarna | 2019-10-15 |
| 10418368 | Buried local interconnect in source/drain region | Bipul C. Paul, Steven R. Soss | 2019-09-17 |
| 10347745 | Methods of forming bottom and top source/drain regions on a vertical transistor device | Puneet Harischandra Suvarna, Daniel Chanemougame | 2019-07-09 |
| 10332969 | Negative capacitance matching in gate electrode structures | Rohit Galatage, Puneet Harischandra Suvarna, Zoran Krivokapic | 2019-06-25 |
| 10312154 | Method of forming vertical FinFET device having self-aligned contacts | Ruilong Xie, Puneet Harischandra Suvarna, Chanro Park, Min Gyu Sung, Lars Liebmann +2 more | 2019-06-04 |
| 10283621 | Method of forming vertical field effect transistors with self-aligned gates and gate extensions and the resulting structure | Ruilong Xie, Lars Liebmann, Hui Zang | 2019-05-07 |
| 10269812 | Forming contacts for VFETs | Ruilong Xie, Lars Liebmann, Daniel Chanemougame, Chanro Park, John H. Zhang +1 more | 2019-04-23 |
| 10256158 | Insulated epitaxial structures in nanosheet complementary field effect transistors | Julien Frougier, Ruilong Xie, Puneet Harischandra Suvarna | 2019-04-09 |
| 10249710 | Methods, apparatus, and system for improved nanowire/nanosheet spacers | Deepak Nayak | 2019-04-02 |
| 10243073 | Vertical channel field-effect transistor (FET) process compatible long channel transistors | Brent A. Anderson, Kwan-Yong Lim, Hiroaki Niimi, Junli Wang | 2019-03-26 |
| 10236379 | Vertical FET with self-aligned source/drain regions and gate length based on channel epitaxial growth process | Puneet Harischandra Suvarna, Julien Frougier, Bartlomiej Jan Pawlak | 2019-03-19 |
| 10236292 | Complementary FETs with wrap around contacts and methods of forming same | Julien Frougier, Ruilong Xie, Puneet Harischandra Suvarna, Hiroaki Niimi, Ali Razavieh | 2019-03-19 |
| 10217846 | Vertical field effect transistor formation with critical dimension control | Ruilong Xie, Min Gyu Sung, Chanro Park, Steven R. Soss, Hui Zang +8 more | 2019-02-26 |
| 10192867 | Complementary FETs with wrap around contacts and method of forming same | Julien Frougier, Ruilong Xie, Puneet Harischandra Suvarna, Hiroaki Niimi, Ali Razavieh | 2019-01-29 |
| 10186577 | Multiple directed self-assembly material mask patterning for forming vertical nanowires | Richard A. Farrell, Gerard Schmid, Ajey Poovannummoottil Jacob | 2019-01-22 |
| 10170617 | Vertical transport field effect transistors | Jiseok Kim, Hiroaki Niimi, Hoon Kim, Puneet Harischandra Suvarna, Jody A. Fronheiser | 2019-01-01 |
| 10170616 | Methods of forming a vertical transistor device | Ruilong Xie, Jody A. Fronheiser | 2019-01-01 |