Issued Patents 2019
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10516064 | Multiple width nanosheet devices | Kangguo Cheng, Lawrence A. Clevenger, Carl Radens, Junli Wang | 2019-12-24 |
| 10510613 | Contact structures | Jiehui Shu, Xusheng Wu, Haigou Huang, Pei Liu, Laertis Economikos | 2019-12-17 |
| 10461186 | Methods of forming vertical field effect transistors with self-aligned contacts and the resulting structures | Ruilong Xie, Mahender Kumar | 2019-10-29 |
| 10438850 | Semiconductor device with local connection | Kangguo Cheng, Lawrence A. Clevenger, Carl Radens, Junli Wang | 2019-10-08 |
| 10438856 | Methods and devices for enhancing mobility of charge carriers | Chengyu Niu, Heng Yang | 2019-10-08 |
| 10431495 | Semiconductor device with local connection | Kangguo Cheng, Lawrence A. Clevenger, Carl Radens, Junli Wang | 2019-10-01 |
| 10431651 | Nanosheet transistor with robust source/drain isolation from substrate | Robin Hsin Kuo Chao, Kangguo Cheng, Cheng Chi, Ruilong Xie | 2019-10-01 |
| 10418272 | Methods, apparatus, and system for a semiconductor device comprising gates with short heights | Jiehui Shu, Garo Derderian, Hui Zang, Haigou Huang, Jinping Liu | 2019-09-17 |
| 10411140 | Integrated cantilever switch | Qing Liu | 2019-09-10 |
| 10411128 | Strained fin channel devices | Kangguo Cheng, Junli Wang, Lawrence A. Clevenger, Carl Radens | 2019-09-10 |
| 10388639 | Self-aligned three dimensional chip stack and method for making the same | Lawrence A. Clevenger, Carl Radens, Yiheng Xu | 2019-08-20 |
| 10388729 | Devices and methods of forming self-aligned, uniform nano sheet spacers | Lawrence A. Clevenger, Kangguo Cheng, Balasubramanian S. Haran | 2019-08-20 |
| 10388659 | Vertical gate-all-around TFET | — | 2019-08-20 |
| 10354921 | Stacked transistors with different channel widths | Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian Pranatharthiharan | 2019-07-16 |
| 10347617 | Self-aligned three dimensional chip stack and method for making the same | Lawrence A. Clevenger, Carl Radens, Yiheng Xu | 2019-07-09 |
| 10325778 | Utilizing multiple layers to increase spatial frequency | Lawrence A. Clevenger, Carl Radens | 2019-06-18 |
| 10325777 | Utilizing multiple layers to increase spatial frequency | Lawrence A. Clevenger, Carl Radens | 2019-06-18 |
| 10325927 | Integrated circuit devices and fabrication techniques | — | 2019-06-18 |
| 10319647 | Semiconductor structure with overlapping fins having different directions, and methods of fabricating the same | Qing Liu | 2019-06-11 |
| 10319630 | Encapsulated damascene interconnect structure for integrated circuits | Lawrence A. Clevenger, Carl Radens, Yiheng Xu | 2019-06-11 |
| 10312261 | Transistor with self-aligned source and drain contacts and method of making same | — | 2019-06-04 |
| 10304815 | Self-aligned three dimensional chip stack and method for making the same | Lawrence A. Clevenger, Carl Radens, Yiheng Xu | 2019-05-28 |
| 10269812 | Forming contacts for VFETs | Ruilong Xie, Lars Liebmann, Daniel Chanemougame, Chanro Park, Steven Bentley +1 more | 2019-04-23 |
| 10256351 | Semi-floating gate FET | Qing Liu | 2019-04-09 |
| 10249496 | Narrowed feature formation during a double patterning process | Jiehui Shu, Xusheng Yu, Xiaoqiang Zhang | 2019-04-02 |