Issued Patents 2019
Showing 1–25 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10505111 | Confined phase change memory with double air gap | Injo Ok, Wei Wang | 2019-12-10 |
| 10490454 | Minimize middle-of-line contact line shorts | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2019-11-26 |
| 10431663 | Method of forming integrated circuit with gate-all-around field effect transistor and the resulting structure | Ruilong Xie, Pietro Montanini, Julien Frougier | 2019-10-01 |
| 10396200 | Method and structure of improving contact resistance for passive and long channel devices | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2019-08-27 |
| 10395995 | Dual liner silicide | Ruilong Xie, Chun-Chen Yeh | 2019-08-27 |
| 10388571 | Fin type field effect transistors with different pitches and substantially uniform fin reveal | Zhenxing Bi, Kangguo Cheng, Thamarai S. Devarajan | 2019-08-20 |
| 10373874 | Middle of the line subtractive self-aligned contacts | Joshua M. Rubin | 2019-08-06 |
| 10361203 | FET trench dipole formation | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2019-07-23 |
| 10355080 | Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2019-07-16 |
| 10354921 | Stacked transistors with different channel widths | Kangguo Cheng, Lawrence A. Clevenger, John H. Zhang | 2019-07-16 |
| 10347632 | Forming spacer for trench epitaxial structures | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2019-07-09 |
| 10347749 | Reducing bending in parallel structures in semiconductor fabrication | Pietro Montanini, John R. Sporre, Ruilong Xie | 2019-07-09 |
| 10347633 | Spacer for trench epitaxial structures | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2019-07-09 |
| 10340189 | Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices | Junli Wang, Ruilong Xie | 2019-07-02 |
| 10325848 | Self-aligned local interconnect technology | Andrew M. Greene, Injo Ok, Charan V. V. S. Surisetty, Ruilong Xie | 2019-06-18 |
| 10304747 | Dual liner silicide | Ruilong Xie, Chun-Chen Yeh | 2019-05-28 |
| 10304741 | Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices | Junli Wang, Ruilong Xie | 2019-05-28 |
| 10297506 | HDP fill with reduced void formation and spacer damage | Huiming Bu, Andrew M. Greene, Ruilong Xie | 2019-05-21 |
| 10276569 | Minimizing shorting between FinFET epitaxial regions | Kangguo Cheng, Alexander Reznicek, Charan V. Surisetty | 2019-04-30 |
| 10256239 | Spacer formation preventing gate bending | Eric R. Miller, Soon-Cheon Seo, John R. Sporre | 2019-04-09 |
| 10256296 | Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2019-04-09 |
| 10249624 | Semiconductor structure containing low-resistance source and drain contacts | Injo Ok, Charan V. Surisetty | 2019-04-02 |
| 10242981 | Fin cut during replacement gate formation | Andrew M. Greene, Sivananda K. Kanakasabapathy, John R. Sporre | 2019-03-26 |
| 10236212 | Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices | Junli Wang, Ruilong Xie | 2019-03-19 |
| 10236253 | Self-aligned local interconnect technology | Andrew M. Greene, Injo Ok, Charan V. V. S. Surisetty, Ruilong Xie | 2019-03-19 |