Issued Patents 2019
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10490454 | Minimize middle-of-line contact line shorts | Injo Ok, Balasubramanian Pranatharthiharan, Charan V. Surisetty | 2019-11-26 |
| 10475886 | Modified fin cut after epitaxial growth | Sivananda K. Kanakasabapathy, Fee Li Lie, Raghavasimhan Sreenivasan | 2019-11-12 |
| 10468498 | Vertical fin bipolar junction transistor with high germanium content silicon germanium base | Seyoung Kim, Choonghyun Lee, Injo Ok | 2019-11-05 |
| 10453844 | Techniques for enhancing vertical gate-all-around FET performance | Injo Ok, Choonghyun Lee, Seyoung Kim | 2019-10-22 |
| 10396126 | Resistive memory device with electrical gate control | Seyoung Kim, Takashi Ando, Choonghyun Lee, Injo Ok | 2019-08-27 |
| 10396200 | Method and structure of improving contact resistance for passive and long channel devices | Injo Ok, Balasubramanian Pranatharthiharan, Charan V. Surisetty | 2019-08-27 |
| 10381462 | Nanowire FET including nanowire channel spacers | — | 2019-08-13 |
| 10381074 | Differential weight reading of an analog memory element in crosspoint array utilizing current subtraction transistors | Seyoung Kim, Injo Ok, Choonghyun Lee | 2019-08-13 |
| 10374066 | Fin and shallow trench isolation replacement to prevent gate collapse | — | 2019-08-06 |
| 10361203 | FET trench dipole formation | Injo Ok, Balasubramanian Pranatharthiharan, Charan V. Surisetty | 2019-07-23 |
| 10355109 | Spacer formation on semiconductor device | Thamarai S. Devarajan, Sanjay C. Mehta, Eric R. Miller | 2019-07-16 |
| 10355080 | Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack | Injo Ok, Balasubramanian Pranatharthiharan, Charan V. Surisetty | 2019-07-16 |
| 10347739 | Extended contact area using undercut silicide extensions | Effendi Leobandung, Tenko Yamashita, Chun-Chen Yeh | 2019-07-09 |
| 10347456 | Vertical vacuum channel transistor with minimized air gap between tip and gate | Injo Ok, Choonghyun Lee, Seyoung Kim | 2019-07-09 |
| 10347632 | Forming spacer for trench epitaxial structures | Injo Ok, Balasubramanian Pranatharthiharan, Charan V. Surisetty | 2019-07-09 |
| 10347633 | Spacer for trench epitaxial structures | Injo Ok, Balasubramanian Pranatharthiharan, Charan V. Surisetty | 2019-07-09 |
| 10325820 | Source and drain isolation for CMOS nanosheet with one block mask | Choonghyun Lee, Injo Ok | 2019-06-18 |
| 10319721 | Spacer for dual epi CMOS devices | — | 2019-06-11 |
| 10297668 | Vertical transport fin field effect transistor with asymmetric channel profile | Choonghyun Lee, Brent A. Anderson, Injo Ok | 2019-05-21 |
| 10297510 | Sidewall image transfer process for multiple gate width patterning | Fee Li Lie, Linus Jang | 2019-05-21 |
| 10256239 | Spacer formation preventing gate bending | Balasubramanian Pranatharthiharan, Eric R. Miller, John R. Sporre | 2019-04-09 |
| 10256296 | Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack | Injo Ok, Balasubramanian Pranatharthiharan, Charan V. Surisetty | 2019-04-09 |
| 10236362 | Nanowire FET including nanowire channel spacers | — | 2019-03-19 |
| 10170499 | FinFET device with abrupt junctions | Kangguo Cheng, Hong He, Ali Khakifirooz, Alexander Reznicek | 2019-01-01 |
| 10170478 | Spacer for dual epi CMOS devices | — | 2019-01-01 |