Issued Patents 2019
Showing 25 most recent of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10522419 | Stacked field-effect transistors (FETs) with shared and non-shared gates | Pouya Hashemi, Choonghyun Lee, Alexander Reznicek, Jingyun Zhang | 2019-12-31 |
| 10504799 | Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap | Martin M. Frank, Renee T. Mo, Vijay Narayanan | 2019-12-10 |
| 10504900 | Enhanced field Resistive RAM integrated with nanosheet technology | Pouya Hashemi, Alexander Reznicek | 2019-12-10 |
| 10505112 | CMOS compatible non-filamentary resistive memory stack | Eduard A. Cartier, Adam M. Pyzyna, John Bruley | 2019-12-10 |
| 10497752 | Resistive random-access memory array with reduced switching resistance variability | Choonghyun Lee, Seyoung Kim, Wilfried E. Haensch | 2019-12-03 |
| 10490559 | Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions | Ruqiang Bao, Pouya Hashemi, Choonghyun Lee | 2019-11-26 |
| 10475997 | Forming resistive memory crossbar array employing selective barrier layer growth | Chih-Chao Yang, Lawrence A. Clevenger | 2019-11-12 |
| 10453792 | High density antifuse co-integrated with vertical FET | Alexander Reznicek, Pouya Hashemi, Miaomiao Wang | 2019-10-22 |
| 10395993 | Methods and structure to form high K metal gate stack with single work-function metal | Balaji Kannan, Siddarth A. Krishnan, Unoh Kwon, Shahab Siddiqui | 2019-08-27 |
| 10396077 | Patterned gate dielectrics for III-V-based CMOS circuits | Martin M. Frank, Renee T. Mo, Vijay Narayanan, John Rozen | 2019-08-27 |
| 10396126 | Resistive memory device with electrical gate control | Seyoung Kim, Choonghyun Lee, Injo Ok, Soon-Cheon Seo | 2019-08-27 |
| 10396146 | Leakage current reduction in stacked metal-insulator-metal capacitors | Hemanth Jagannathan, Paul C. Jamison, John Rozen | 2019-08-27 |
| 10388727 | Stacked indium gallium arsenide nanosheets on silicon with bottom trapezoid isolation | Pouya Hashemi, Mahmoud Khojasteh, Alexander Reznicek | 2019-08-20 |
| 10381433 | Leakage current reduction in stacked metal-insulator-metal capacitors | Hemanth Jagannathan, Paul C. Jamison, John Rozen | 2019-08-13 |
| 10381438 | Vertically stacked NFETS and PFETS with gate-all-around structure | Jingyun Zhang, Pouya Hashemi, Choonghyun Lee, Alexander Reznicek | 2019-08-13 |
| 10381563 | Resistive memory crossbar array compatible with Cu metallization | Michael Rizzolo, Lawrence A. Clevenger, Shyng-Tsong Chen | 2019-08-13 |
| 10381431 | Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS back-end | Martin M. Frank, Xiao Sun, Jin-Ping Han, Vijay Narayanan | 2019-08-13 |
| 10381561 | Dedicated contacts for controlled electroforming of memory cells in resistive random-access memory array | Lawrence A. Clevenger, Chih-Chao Yang, Benjamin D. Briggs | 2019-08-13 |
| 10377370 | Hybrid vehicle | Yu Shimizu, Takeshi Kishimoto, Masaya Amano | 2019-08-13 |
| 10373835 | Method of lateral oxidation of nFET and pFET high-K gate stacks | Robert H. Dennard, Martin M. Frank | 2019-08-06 |
| 10374039 | Enhanced field bipolar resistive RAM integrated with FDSOI technology | Pouya Hashemi, Alexander Reznicek | 2019-08-06 |
| 10366323 | Crossbar resistive memory array with highly conductive copper/copper alloy electrodes and silver/silver alloys electrodes | Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe | 2019-07-30 |
| 10366897 | Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer | Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan | 2019-07-30 |
| 10361368 | Confined lateral switching cell for high density scaling | Robert L. Bruce, John Rozen | 2019-07-23 |
| 10361132 | Structures with thinned dielectric material | Ruqiang Bao, Aritra Dasgupta, Kai Zhao, Unoh Kwon, Siddarth A. Krishnan | 2019-07-23 |