Issued Patents 2019
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10373942 | Logic layout with reduced area and method of making the same | Ram Asra, Edward J. Nowak, Kota V. R. M. Murali | 2019-08-06 |
| 10366897 | Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer | Takashi Ando, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan | 2019-07-30 |
| 10347494 | Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer | Takashi Ando, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan | 2019-07-09 |
| 10319596 | Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer | Takashi Ando, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan | 2019-06-11 |
| 10170576 | Stable work function for narrow-pitch devices | Takashi Ando, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan | 2019-01-01 |