Issued Patents 2019
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10373942 | Logic layout with reduced area and method of making the same | Mohit Bajaj, Edward J. Nowak, Kota V. R. M. Murali | 2019-08-06 |
| 10374068 | Tunnel field effect transistors | Harald Gossner, Ramgopal Rao | 2019-08-06 |
| 10325824 | Methods, apparatus and system for threshold voltage control in FinFET devices | Mitsuhiro Togo, Xing Zhang, Palanivel Balasubramaniam | 2019-06-18 |